[PATCH] bsps/arm: Fix start in hypervisor mode

[Sebastian Huber]

Only clear the HSCTLR[TE] bit to take exceptions in A32 state.  Keep the
other HSCTLR bits as is since they control the current execution.
Assume that the chip or boot loader did initialize this register
correctly.

Add comments.
---
 bsps/arm/shared/start/start.S | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
index 32b168917a..c7fad5ae58 100644
--- a/bsps/arm/shared/start/start.S
+++ b/bsps/arm/shared/start/start.S
@@ -249,22 +249,25 @@ _start:
 	mov	sp, r3
 	sub	r3, r3, r1
 
+	/* Set HVBAR */
 	ldr	r0, =bsp_start_hyp_vector_table_begin
 	mcr	p15, 4, r0, c12, c0, 0
 
+	/* Set HVC, HCPTR, and HSTR to zero */
 	mov	r0, #0
 	mcr	p15, 4, r0, c1, c1, 0
 	mcr	p15, 4, r0, c1, c1, 2
 	mcr	p15, 4, r0, c1, c1, 3
-/*
- * HSCTLR.TE
- * optional start of hypervisor handlers in Thumb mode
- *	orr	r0, #(1 << 30)
- */
-	mcr	p15, 4, r0, c1, c0, 0	/* HSCTLR */
-	mrc	p15, 4, r0, c1, c1, 1	/* HDCR */
-	and	r0, #0x1f		/* Preserve HPMN */
-	mcr	p15, 4, r0, c1, c1, 1	/* HDCR */
+
+	/* Clear HSCTLR[TE] to take exceptions in A32 state */
+	mrc	p15, 4, r0, c1, c0, 0
+	bic	r0, #(1 << 30)
+	mcr	p15, 4, r0, c1, c0, 0
+
+	/* Set HDCR to zero except HDCR[HPMN] */
+	mrc	p15, 4, r0, c1, c1, 1
+	and	r0, #0x1f
+	mcr	p15, 4, r0, c1, c1, 1
 
 	/* Prepare SVC mode for eret */
 	mrs	r0, cpsr
-- 
2.35.3