[PATCH v2 0/4] Microchip PolarFire SoC support
Joel Sherrill
joel at rtems.org
Wed Sep 21 11:47:48 UTC 2022
Chris did you add it to the bsp-builder configuration?
On Tue, Sep 20, 2022, 11:51 PM <Padmarao.Begari at microchip.com> wrote:
> Hi Joel,
>
> > On Tue, 2022-09-20 at 12:03 -0500, Joel Sherrill wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> > I have pushed this patch set. Please check that the merge is OK and
> > follow up with an update to the Users Guide for those looking for
> > this BSP.
> >
>
> Thank You.
>
> I have checked the merge is OK. Sure, will update the User Guide for
> this BSP.
>
> Thanks & Regards
> Padmarao
>
> > Thanks.
> >
> > On Tue, Sep 20, 2022 at 8:56 AM Joel Sherrill <
> > joel.sherrill at gmail.com> wrote:
> > > This procedure should be added to the Users Guide under the BSPs
> > > section.
> > >
> > > Otherwise, it looks like I should coordinate with Padmarao to make
> > > sure it's ok after I merged it
> > >
> > > On Tue, Sep 20, 2022, 1:50 AM <Padmarao.Begari at microchip.com>
> > > wrote:
> > > > RTEMS SMP on the Microchip PolarFire Icicle Kit
> > > >
> > > > Test Procedure:
> > > >
> > > > 1. Create the "config.ini" file with below content at rtems root
> > > >
> > > > [riscv/mpfs64imafdc]
> > > > BUILD_TESTS = True
> > > > RTEMS_POSIX_API=True
> > > > RTEMS_SMP = True
> > > > BSP_START_COPY_FDT_FROM_U_BOOT=False
> > > > BSP_VERBOSE_FATAL_EXTENSION = False
> > > >
> > > > 2. Build RTEMS
> > > > $ ./waf configure --prefix=$HOME/rtems-start/rtems/6
> > > > $ ./waf
> > > >
> > > > 3. Convert .exe to .elf file
> > > >
> > > > $ riscv-rtems6-objcopy
> > > > build/riscv/mpfs64imafdc/testsuites/smptests/sm
> > > > p01.exe
> > > > build/riscv/mpfs64imafdc/testsuites/smptests/smp01.elf
> > > >
> > > > 4. Generate the payload for the smp01.elf using the hss-payload-
> > > > generator with hart-entry-points/exec-addr: 0x1000000000
> > > >
> > > >
> https://github.com/polarfire-soc/hart-software-services/tree/master/tools/hss-payload-generator
> > > >
> > > > 5. Programming the'payload.bin' for the eMMC/SD
> > > >
> > > > 5.1) Board setting and FPGA Programing
> > > >
> > > >
> https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
> > > >
> > > >
> > > > 5.2). Power Cycle the Microchip PolarFire Icicle Kit and stop at
> > > > the
> > > > HSS.
> > > >
> > > > 5.3) type "mmc" and then "usbdmsc" on the HSS terminal(UART0).
> > > >
> > > > 5.4) Load payload from the Host PC.
> > > > $ sudo dd if=payload.bin of=/dev/sdb bs=512
> > > >
> > > > 5.5) Quit USB and Reset the Icicle Kit
> > > >
> > > > 5.6) Serial terminal UART1 displays the SMP example messages
> > > >
> > > > *** BEGIN OF TEST SMP 1 ***
> > > > *** TEST VERSION: 6.0.0.ef33f861e16de9bf4190a36e4d18062c7300986c
> > > > *** TEST STATE: EXPECTED_PASS
> > > > *** TEST BUILD: RTEMS_POSIX_API RTEMS_SMP
> > > > *** TEST TOOLS: 12.1.1 20220622 (RTEMS 6, RSB
> > > > 3cb78b0b815ba05d17f5c6
> > > > 5865d246a8333aa087, Newlib ea99f21)
> > > >
> > > > CPU 3 start task TA0
> > > > CPU 2 running Task TA0
> > > > CPU 3 start task TA1
> > > > CPU 1 running Task TA1
> > > > CPU 3 start task TA2
> > > > CPU 0 running Task TA2
> > > >
> > > > *** END OF TEST SMP 1 ***
> > > >
> > > > Regards
> > > > Padmarao
> > > > On Mon, 2022-09-19 at 18:30 +0530, Padmarao Begari wrote:
> > > > > This patch set adds the Microchip PolarFire SoC BSP Variant
> > > > > support to RISC-V RTEMS.
> > > > >
> > > > > The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and
> > > > > a 64-bit RISC-V E51 monitor core SoC from Microchip, more
> > > > > info available here:
> > > > > https://www.microchip.com/en-us/products/fpgas-and-plds/
> > > > > system-on-chip-fpgas/polarfire-soc-fpgas#Overview
> > > > >
> > > > > This new BSP variant is added for the 4x U54 cores not for E51
> > > > > because the E51 monitor core is resreved for first stage
> > > > > bootloader (Hart Software Services).
> > > > >
> > > > > The boot HARTID configurable is implemented for the riscv BSP
> > > > > to work with individual hart(cpu core) or SMP.
> > > > >
> > > > > This BSP support components: 4 CPU Cores (U54), Interrupt
> > > > > controller (PLIC), Timer (CLINT), UART (16550-compatible)
> > > > > work fine on actual Microchip PolarFire SoC Icicle Kit.
> > > > >
> > > > > v2:
> > > > > - Add a license and copyright information in dtb header file
> > > > > - Use RISCV_BOOT_HARDID instead of RTEMS_BOOT_HARDID
> > > > > - Add '_RISCV_Map_hardid_to_cpu_index()' and
> > > > > '_RISCV_Map_cpu_index_to_hardid()' functions
> > > > > - Change bsp_fdt_get() instead of bsp_fdt_copy() function for
> > > > dtb
> > > > > - Move dtb and dtb header configurable build option to the bsps
> > > > >
> > > > > Padmarao Begari (4):
> > > > > bsps/riscv: Add device tree blob
> > > > > spec/build/bsps: Add dtb support
> > > > > bsps/riscv: Add Microchip PolarFire SoC BSP variant
> > > > > bsps/shared/: Use device tree blob
> > > > >
> > > > > bsps/riscv/riscv/clock/clockdrv.c | 6 +-
> > > > > bsps/riscv/riscv/config/mpfs64imafdc.cfg | 9 +
> > > > > bsps/riscv/riscv/dts/mpfs.dts | 365
> > > > +++++++++++
> > > > > bsps/riscv/riscv/include/bsp/mpfs-dtb.h | 602
> > > > > ++++++++++++++++++
> > > > > bsps/riscv/riscv/include/bsp/riscv.h | 14 +
> > > > > bsps/riscv/riscv/irq/irq.c | 81 +++
> > > > > bsps/riscv/riscv/start/bsp_fatal_halt.c | 3 +
> > > > > bsps/riscv/riscv/start/bspsmp.c | 2 +-
> > > > > bsps/riscv/riscv/start/bspstart.c | 19 +-
> > > > > bsps/riscv/shared/start/start.S | 2 +
> > > > > bsps/shared/start/bsp-fdt.c | 8 +
> > > > > .../score/cpu/riscv/include/rtems/score/cpu.h | 2 +-
> > > > > .../cpu/riscv/include/rtems/score/cpuimpl.h | 2 +-
> > > > > spec/build/bsps/optdtb.yml | 19 +
> > > > > spec/build/bsps/optdtbheaderpath.yml | 20 +
> > > > > spec/build/bsps/riscv/optextirqmax.yml | 5 +-
> > > > > spec/build/bsps/riscv/optrambegin.yml | 5 +-
> > > > > spec/build/bsps/riscv/optramsize.yml | 5 +-
> > > > > spec/build/bsps/riscv/riscv/abi.yml | 6 +
> > > > > .../bsps/riscv/riscv/bspmpfs64imafdc.yml | 19 +
> > > > > spec/build/bsps/riscv/riscv/grp.yml | 6 +
> > > > > spec/build/bsps/riscv/riscv/optmpfs.yml | 18 +
> > > > > spec/build/bsps/riscv/riscv/optns16550max.yml | 3 +
> > > > > spec/build/cpukit/cpuopts.yml | 2 +
> > > > > spec/build/cpukit/optarchbits.yml | 1 +
> > > > > spec/build/cpukit/optboothartid.yml | 19 +
> > > > > spec/build/cpukit/optsmp.yml | 1 +
> > > > > 27 files changed, 1235 insertions(+), 9 deletions(-)
> > > > > create mode 100644 bsps/riscv/riscv/config/mpfs64imafdc.cfg
> > > > > create mode 100644 bsps/riscv/riscv/dts/mpfs.dts
> > > > > create mode 100644 bsps/riscv/riscv/include/bsp/mpfs-dtb.h
> > > > > create mode 100644 spec/build/bsps/optdtb.yml
> > > > > create mode 100644 spec/build/bsps/optdtbheaderpath.yml
> > > > > create mode 100644
> > > > spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml
> > > > > create mode 100644 spec/build/bsps/riscv/riscv/optmpfs.yml
> > > > > create mode 100644 spec/build/cpukit/optboothartid.yml
> > > > >
> > > > _______________________________________________
> > > > devel mailing list
> > > > devel at rtems.org
> > > > http://lists.rtems.org/mailman/listinfo/devel
> > > >
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/devel/attachments/20220921/cd37bfca/attachment.htm>
More information about the devel
mailing list