CVA6 RISC-V support

[EYSSARTIER Kevin]

Classified as: {THALES GROUP LIMITED DISTRIBUTION}

Hello,

I am working on the port of RTEMS 6 on our RISC-V processor, the CORE-V CVA6 processor
GitHub - ThalesGroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux<https://github.com/ThalesGroup/cva6>
The port is working and I think it is a good idea to publish my work on the official repository.
During the port I also found two bugs in the RISC-V generic BSP that I corrected.

I hope it satisfy the quality standards of RTEMS.
Best regards,
-------
Kevin EYSSARTIER, Research Engineer
Thales Research & Technology France - High Performance Computing Lab
Campus Polytechnique - 1, avenue Augustin Fresnel  - 91767 Palaiseau cedex
Phone : +33 (0)1 69 41 55 14  Internal : 341 55 14



{THALES GROUP LIMITED DISTRIBUTION}
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