CVA6 RISC-V support

Joel Sherrill joel at rtems.org
Tue Aug 1 18:54:13 UTC 2023


Thanks for the submission. It's a bit hard to review with the patches as
attachments rather than having been sent via git send-email but here goes.

Hopefully someone with more RISC-V knowledge can comment also.


0001 - long comment appears to be one line. Please break into multiple
lines.

0001 - riscv/abi.yml is this just adding another set of compiler options?
Hard to tell.

0001 - bspcv32a6.yml - Did this file end up with a copyright?

0002 - same issue with long comment. Blank line between paragraphs.

0002 - Is this a common issue which applies to other BSPs?

0002 - Is there a maximum length of the strings so strnlen() can be used
instead of strlen()?

0002 - Call strlen/strnlen once on stdout_patch and assign to a variable of
type size_t

0003 - This looks like it will break every other architecture since they
will not have had restart renamed to start.
Can you explain what is really not working so we can find a solution that
is strictly within the RISC-V? There is
also a context method which is invoked in the context of the thread once it
begins execution. Maybe this will
work. See threadhandler.c for the call
to _Context_Initialization_at_thread_begin.

I personally am ok for 01 and 02. 03 will require discussion.

--joel


On Tue, Aug 1, 2023 at 10:53 AM EYSSARTIER Kevin <
kevin.eyssartier at thalesgroup.com> wrote:

> Classified as: {THALES GROUP LIMITED DISTRIBUTION}
>
> Hello,
>
>
>
> I am working on the port of RTEMS 6 on our RISC-V processor, the CORE-V
> CVA6 processor
>
> GitHub - ThalesGroup/cva6: The CORE-V CVA6 is an Application class 6-stage
> RISC-V CPU capable of booting Linux <https://github.com/ThalesGroup/cva6>
>
> The port is working and I think it is a good idea to publish my work on
> the official repository.
>
> During the port I also found two bugs in the RISC-V generic BSP that I
> corrected.
>
>
>
> I hope it satisfy the quality standards of RTEMS.
>
> Best regards,
>
> -------
>
> Kevin EYSSARTIER, Research Engineer
>
> Thales Research & Technology France – High Performance Computing Lab
> Campus Polytechnique - 1, avenue Augustin Fresnel  - 91767 Palaiseau cedex
> Phone : +33 (0)1 69 41 55 14  Internal : 341 55 14
>
>
>
> {THALES GROUP LIMITED DISTRIBUTION}
> _______________________________________________
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