bsps/xilinx-zynqmp : Add BSP for RPU

[Kinsey Moore]

Overall, this looks like great work! Thanks for contributing!

Just a couple of addons to Joel's comments below.

On Wed, Jun 14, 2023 at 8:49 AM Joel Sherrill <joel at rtems.org> wrote:

>
> On Wed, Jun 14, 2023 at 3:08 AM Philip Kirkpatrick <
> p.kirkpatrick at reflexaerospace.com> wrote:
>
> diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/xttcps_hw.h
>> b/bsps/arm/xilinx-zynqmp/include/bsp/xttcps_hw.h
>> new file mode 100644
>> index 0000000000..ba0d559b07
>> --- /dev/null
>> +++ b/bsps/arm/xilinx-zynqmp/include/bsp/xttcps_hw.h
>> @@ -0,0 +1,223 @@
>>
>> +/******************************************************************************
>> +* Copyright (C) 2010 - 2021 Xilinx, Inc.  All rights reserved.
>> +* SPDX-License-Identifier: MIT
>>
>> +******************************************************************************/
>>
>
> Someone else should comment on whether this Xilinx file should be in
> a location where it is shareable by other BSPs.
>

This should definitely be moved into a shared location. It's theoretically
usable by ARM, AArch64, and Microblaze on this platform.

>
> Is this file unmodified from the Xilinx provided version? Changes for
> RTEMS should be inside conditional like "#ifdef __rtems__" or
> "#ifndef __rtems__"
>
>
>> +#ifndef LIBBSP_ARM_ZYNQMP
>> +#define LIBBSP_ARM_ZYNQMP
>> +
>> +/* Data derived from
>> https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PS-I/O-Peripherals-Registers
>> */
>> +
>> +/* LPD IO Peripherals */
>> +#define ZYNQMP_UART0 (0xFF000000)
>>
>
> I'm assuming that these constants do not need to be marked as unsigned.
>
>
>> +#define ZYNQMP_UART1 (0xFF010000)
>> +#define ZYNQMP_I2C0 (0xFF020000)
>> +#define ZYNQMP_I2C1 (0xFF030000)
>> +#define ZYNQMP_SPI0 (0xFF040000)
>> +#define ZYNQMP_SPI1 (0xFF050000)
>> +#define ZYNQMP_CAN0 (0xFF060000)
>> +#define ZYNQMP_CAN1 (0xFF070000)
>> +#define ZYNQMP_GPIO (0xFF0A0000)
>> +#define ZYNQMP_GEM0 (0xFF0B0000)
>> +#define ZYNQMP_GEM1 (0xFF0C0000)
>> +#define ZYNQMP_GEM2 (0xFF0D0000)
>> +#define ZYNQMP_GEM3 (0xFF0E0000)
>> +#define ZYNQMP_QSPI (0xFF0F0000)
>> +#define ZYNQMP_NAND (0xFF100000)
>> +#define ZYNQMP_SD0 (0xFF160000)
>> +#define ZYNQMP_SD1 (0xFF170000)
>> +#define ZYNQMP_IPI_MSG (0xFF990000)
>> +#define ZYNQMP_USB0 (0xFF9D0000)
>> +#define ZYNQMP_USB1 (0xFF9E0000)
>> +#define ZYNQMP_AMS (0xFFA50000)
>> +#define ZYNQMP_PSSYSMON (0xFFA50800)
>> +#define ZYNQMP_PLSYSMON (0xFFA50C00)
>> +#define ZYNQMP_CSU_SWDT (0xFFCB0000)
>> +
>> +/* FPD IO Peripherals */
>> +#define ZYNQMP_SATA (0xFD0C0000)
>> +#define ZYNQMP_PCIE (0xFD0E0000)
>> +#define ZYNQMP_PCIE_IN (0xFD0E0800)
>> +#define ZYNQMP_PCIE_EG (0xFD0E0C00)
>> +#define ZYNQMP_PCIE_DMA (0xFD0F0000)
>> +#define ZYNQMP_SIOU (0xFD3D0000)
>> +#define ZYNQMP_GTR (0xFD400000)
>> +#define ZYNQMP_PCIE_ATTR (0xFD480000)
>> +#define ZYNQMP_DP (0xFD4A0000)
>> +#define ZYNQMP_GPU (0xFD4B0000)
>> +#define ZYNQMP_DP_DMA (0xFD4C0000)
>> +
>> +/* LPD System Registers */
>> +#define ZYNQMP_IPI (0xFF300000)
>> +#define ZYNQMP_TTC0 (0xFF110000)
>> +#define ZYNQMP_TTC1 (0xFF120000)
>> +#define ZYNQMP_TTC2 (0xFF130000)
>> +#define ZYNQMP_TTC3 (0xFF140000)
>> +#define ZYNQMP_LPD_SWDT (0xFF150000)
>> +#define ZYNQMP_XPPU (0xFF980000)
>> +#define ZYNQMP_XPPU_SINK (0xFF9C0000)
>> +#define ZYNQMP_PL_LPD (0xFF9B0000)
>> +#define ZYNQMP_OCM (0xFFA00000)
>> +#define ZYNQMP_LPD_FPD (0xFFA10000)
>> +#define ZYNQMP_RTC (0xFFA60000)
>> +#define ZYNQMP_OCM_XMPU (0xFFA70000)
>> +#define ZYNQMP_LPD_DMA (0xFFA80000)
>> +#define ZYNQMP_CSU_DMA (0xFFC80000)
>> +#define ZYNQMP_CSU (0xFFCA0000)
>> +#define ZYNQMP_BBRAM (0xFFCD0000)
>> +
>> +#endif /* LIBBSP_ARM_ZYNQMP */
>>
>
> If we're going to have a list of peripheral addresses for the platform, it
might be useful to have in a shared space for the same reason as the TTC.
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