[PATCH] bsps/riscv: Clear interrupt complete before disable

[Padmarao.Begari at microchip.com]

> On Mon, 2023-03-06 at 14:11 +0100, Sebastian Huber wrote:
> 
> On 06.03.23 13:00, Padmarao.Begari at microchip.com wrote:
> > > On Mon, 2023-03-06 at 11:19 +0100, Sebastian Huber wrote:
> > > 
> > > On 06.03.23 10:24,Padmarao.Begari at microchip.com  wrote:
> > > > Hi Sebastian,
> > > > 
> > > > > On Mon, 2023-03-06 at 09:41 +0100, Sebastian Huber wrote:
> > > > > 
> > > > > On 06.03.23 09:37,Padmarao.Begari at microchip.com  wrote:
> > > > > > > Is
> > > > > > > the claim complete message ignored if the interrupt is
> > > > > > > disabled?
> > > > > > > 
> > > > > > Yes.
> > > > > Is this an intended and documented behaviour of the PLIC?
> > > > Not documented
> > > Is this a common PLIC behaviour or just the case for the
> > > MicroChip
> > > implementation?
> > > 
> > It's a common PLIC behaviour.
> 
> It is not implemented in the Qemu PLIC emulation:
> 
> https://github.com/qemu/qemu/blob/master/hw/intc/sifive_plic.c#L242
> 
> Where do I see this behaviour in a PLIC implementation, for example:
> 
> https://github.com/lowRISC/opentitan/tree/master/hw/ip_templates/rv_plic
> 
> That the interrupt completion depends on the interrupt enable/disable
> status is quite unusual.
> 

I will look into above links, mean while you can check the implemention
of external interrupt service in the PolarFire SoC with same the siFive
PLIC core.

https://github.com/polarfire-soc/hart-software-services/blob/master/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/mss_mtrap.c#L623

Regards
Padmarao
  
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