[PATCH] bsps/riscv: Clear interrupt complete before disable

[Padmarao.Begari at microchip.com]

Hi Sebastian,

>On Mon, 2023-03-06 at 14:11 +0100, Sebastian Huber wrote:
> 
> 
> On 06.03.23 13:00, Padmarao.Begari at microchip.com wrote:
> > > On Mon, 2023-03-06 at 11:19 +0100, Sebastian Huber wrote:
> > > 
> > > On 06.03.23 10:24,Padmarao.Begari at microchip.com  wrote:
> > > > Hi Sebastian,
> > > > 
> > > > > On Mon, 2023-03-06 at 09:41 +0100, Sebastian Huber wrote:
> > > > > 
> > > > > On 06.03.23 09:37,Padmarao.Begari at microchip.com  wrote:
> > > > > > > Is
> > > > > > > the claim complete message ignored if the interrupt is
> > > > > > > disabled?
> > > > > > > 
> > > > > > Yes.
> > > > > Is this an intended and documented behaviour of the PLIC?
> > > > Not documented
> > > Is this a common PLIC behaviour or just the case for the
> > > MicroChip
> > > implementation?
> > > 
> > It's a common PLIC behaviour.
> 
> It is not implemented in the Qemu PLIC emulation:
> 
> https://github.com/qemu/qemu/blob/master/hw/intc/sifive_plic.c#L242
> 
> Where do I see this behaviour in a PLIC implementation, for example:
> 
> https://github.com/lowRISC/opentitan/tree/master/hw/ip_templates/rv_plic
> 
> That the interrupt completion depends on the interrupt enable/disable
> status is quite unusual.
> 

https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#8-interrupt-completion
The interrupt is completed only when the interrupt is enabled but not
when disabled.

Can we clear the interrupt before calling the interrupt handler? like
below
https://github.com/RTEMS/rtems/blob/master/bsps/riscv/riscv/irq/irq.c#L90

    while ((interrupt_index = plic_hart_regs->claim_complete) != 0) {
+     plic_hart_regs->claim_complete = interrupt_index;
      bsp_interrupt_handler_dispatch(
        RISCV_INTERRUPT_VECTOR_EXTERNAL(interrupt_index)
      );

-      plic_hart_regs->claim_complete = interrupt_index;

Also refer 
https://github.com/psherman42/Demonstrating-MTVEC/blob/main/start.s#L307

Regards
Padmarao

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