[PATCH v2 0/4] Add ZynqMP Cortex-R5 BSP

[Kinsey Moore]

Great! I'll get those integrated and post a v3.

Thanks,
Kinsey

On Tue, Oct 24, 2023 at 9:10 AM Philip Kirkpatrick <
p.kirkpatrick at reflexaerospace.com> wrote:

> Kinsey,
>
> I looked this over and built and tested it on actual hardware.  I made the
> minor changes below, but afterwards it worked as expected.  The change to
> `bspmercuryxu5.yml` was required to allow my application to find
> `peripheral_maps/xilinx_zynqmp.h`.  The other changes were not required,
> but cleaned up some warnings.
>
> ---
>  bsps/arm/xilinx-zynqmp-rpu/include/bsp.h                | 2 +-
>  bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c          | 6 +++---
>  spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml | 4 +++-
>  3 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
> b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
> index db3997677f..e386bd4b26 100644
> --- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
> +++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
> @@ -81,7 +81,7 @@ extern "C" {
>   *
>   * Provide in the application to override the defaults in the BSP.
>   */
> -BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
> +BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void);
>
>  void zynqmp_debug_console_flush(void);
>
> diff --git a/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
> b/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
> index 7c927058f7..8c591890bf 100644
> --- a/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
> +++ b/bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
> @@ -123,19 +123,19 @@ static BSP_START_TEXT_SECTION void
> zynqmp_configure_mpu_sections(void)
>    Xil_SetMPURegion(addr, size, attrib);
>
>    // Add RO region for RO section
> -  addr = bsp_section_rodata_begin;
> +  addr = (u32)bsp_section_rodata_begin;
>    size = bsp_section_rodata_end - bsp_section_rodata_begin;
>    attrib = NORM_NSHARED_WB_WA | PRIV_RO_USER_RO;
>    Xil_SetMPURegion(addr, size, attrib);
>
>    // Add no cache region for no cache section
> -  addr = bsp_section_nocache_begin;
> +  addr = (u32)bsp_section_nocache_begin;
>    size = bsp_section_nocache_end - bsp_section_nocache_begin;
>    attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
>    Xil_SetMPURegion(addr, size, attrib);
>
>    // Add no cache region for no cache no load section
> -  addr = bsp_section_nocachenoload_begin;
> +  addr = (u32)bsp_section_nocachenoload_begin;
>    size = bsp_section_nocachenoload_end - bsp_section_nocachenoload_begin;
>    attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
>    Xil_SetMPURegion(addr, size, attrib);
> diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
> b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
> index 342cfdea57..595c1ad507 100644
> --- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
> +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
> @@ -16,10 +16,12 @@ install:
>    source:
>    - bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
>    - bsps/include/dev/clock/xttcps_hw.h
> -  - bsps/include/peripheral_maps/xilinx_zynqmp.h
>  - destination: ${BSP_INCLUDEDIR}/bsp
>    source:
>    - bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
> +- destination: ${BSP_INCLUDEDIR}/peripheral_maps
> +  source:
> +  - bsps/include/peripheral_maps/xilinx_zynqmp.h
>  links:
>  - role: build-dependency
>    uid: ../grp
> --
>
>
> On Fri, Oct 20, 2023 at 7:03 PM Kinsey Moore <kinsey.moore at oarcorp.com>
> wrote:
>
>> Philip,
>> When you get a chance, could you verify that this refactoring meets your
>> expectations as far as functionality? I'm especially interested in whether
>> the timer interrupts behave as you expect them to on hardware. I don't mind
>> getting the Xilinx support code updates committed, but I'd like some
>> feedback on the BSP itself.
>>
>> Kinsey
>>
>> On Thu, Oct 12, 2023 at 12:02 PM Kinsey Moore <kinsey.moore at oarcorp.com>
>> wrote:
>>
>>> Changes from v1 (originally submitted by Philip Kirkpatrick):
>>> Refactoring:
>>> * import Xilinx code before modification
>>> * better use the existing Xilinx support code
>>> Other:
>>> * An additional patch to add cache support (also from Philip) has been
>>>   integrated and refactored
>>>
>>> This has been tested on Xilinx's QEMU with Xilinx's device tree
>>> definitions using the following command line options to QEMU:
>>> -no-reboot -nographic -M arm-generic-fdt -serial null -serial mon:stdio \
>>> -device loader,file=<RTEMS exe path>,cpu-num=4 \
>>> -device loader,addr=0xff5e023c,data=0x80088fde,data-len=4 \
>>> -device loader,addr=0xff9a0000,data=0x80000218,data-len=4 \
>>> -hw-dtb <XLNX DTB dir>/LATEST/SINGLE_ARCH/board-zynqmp-zcu102.dtb \
>>> -m 4096 -display none
>>>
>>> hello.exe and ts-validation-cache.exe operated as expected. Ticker
>>> produced output, but the timing and content was incorrect on QEMU.
>>>
>>>
>>> _______________________________________________
>>> devel mailing list
>>> devel at rtems.org
>>> http://lists.rtems.org/mailman/listinfo/devel
>>>
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