[PATCH v2 2/3] dev/serial: Add ZYNQ_UART_[01]_BASE_ADDR

[Chris Johns]

On 4/4/2024 8:19 pm, Sebastian Huber wrote:
> On 28.03.24 16:48, Kinsey Moore wrote:
>> This patch set looks good to me. I'd suggest a different file for the versal
>> unless there's a good name that can easily cover both.
> 
> The versal BSP doesn't use this driver and seems to have a different hardware
> UART interface. It uses a BSP-specific driver:
> 
> ./bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart-regs.h
> ./bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart.h
> ./bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c
> ./bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c
> 
> I don't think we should mix these two currently independent drivers.
> 

Ah yes and thanks. I think the Versal UART is based on ARM IP that XIlinx has
modified. It is even worse to handle as the TX FIFO trigger does not work as
expected. It needs to have half the TX FIFO loaded before TX interrupts work.

Chris