RFC: Add API to get and set interrupt priorities for interrupt vectors

Sebastian Huber sebastian.huber at embedded-brains.de
Mon Mar 25 08:17:23 UTC 2024


On 21.03.24 20:28, Gedare Bloom wrote:
> Two basic questions:
> 
> Does the priority field type need to be Architecture- or BSP-defined
> or is uint32_t always going to be fine.

In theory, the priority range depends on the interrupt controller 
implementation. However, an uint32_t should be more than enough. The 
maximum priority value defines also the maximum interrupt nesting depth. 
So, even 256 interrupt priority levels would be quite a lot.

> 
> Does changing (increasing) the priority of a vector from within
> interrupt context possibly cause a pending interrupt to post that was
> previously at a lower priority than the currently masked priority
> level? In that case, it would cause a preemption to occur. I'm
> guessing this behavior could be architecture-specific.

This behaviour is entirely interrupt-controller specific. Changing the 
priority while an interrupt is active is usually a bad idea since this 
can confuse the hardware interrupt priority stack. I guess we have to 
add some interrupt-controller specific information to the notes, for 
example:

For the Armv7-M NVIC, there are 256 priority levels supported.  The 
granularity of the priority levels depends on the interrupt controller 
configuration.  Some lower bits of a priority value may be read-as-zero. 
Interrupts with a priority value less than 128 are not disabled by the 
RTEMS interrupt disable directive. Such interrupts shall not use 
operating system services.

For the Arm GICv2, ...

For the Arm GICv3, ...

> 
> I added those questions to the ticket also.
> Gedare
> 
> On Wed, Mar 20, 2024 at 2:59 AM Sebastian Huber
> <sebastian.huber at embedded-brains.de> wrote:
>>
>> Hello,
>>
>> I added a ticket for a proposal for an API to get and set interrupt
>> priorities for interrupt vectors:
>>
>> https://devel.rtems.org/ticket/5002
>>
>> I would like to implement this API at least for the BSPs using the
>> ARM/AArch64 GIC.
>>
>> --
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-- 
embedded brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.huber at embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
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