Improvements to SMP under the arch64 architecture

[Sebastian Huber]

On 08.05.24 08:17, Sebastian Huber wrote:
> Hello,
> 
> on the arm target, we use this:
> 
> static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( 
> void )
> {
>    struct Per_CPU_Control *cpu_self;
> 
>    /* Use PL1 only Thread ID Register (TPIDRPRW) */
>    __asm__ volatile (
>      "mrc p15, 0, %0, c13, c0, 4"
>      : "=r" ( cpu_self )
>    );
> 
>    return cpu_self;
> }
> 
> to access the per-CPU control. I guess, AArch64 has also a thread ID 
> register available for operating system use. With this we could 
> implement _CPU_Get_current_processor() like this:
> 
> return _Per_CPU_Get_index( _CPU_Get_current_per_CPU_control() );
> 
> The BSP-specific startup code has to decode the MPIDR and set the thread 
> ID register accordingly.

If we assume that we always run in EL1 or higher, then we can use the 
TPIDR_EL1 for an _AArch64_Get_current_per_CPU_control().

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