[PATCH 1/6] BBB: am335x.h: Add defines for MMC0 interface, AM335x MMC/SD registers, and CMD/responses
Jarielle Catbagan
jcatbagan93 at gmail.com
Mon Aug 3 04:16:38 UTC 2015
---
ports/beagleboneblack/am335x.h | 256 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 252 insertions(+), 4 deletions(-)
diff --git a/ports/beagleboneblack/am335x.h b/ports/beagleboneblack/am335x.h
index 55a4d2a..8b85b4b 100644
--- a/ports/beagleboneblack/am335x.h
+++ b/ports/beagleboneblack/am335x.h
@@ -266,6 +266,9 @@
/*===========================================================================*/
#define CM_PER_L3_CLKSTCTRL 0x0C
#define CM_PER_EMIF_CLKCTRL 0x28
+#define CM_PER_MMC0_CLKCTRL 0x3C
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE 0x02
+#define CM_PER_MMC0_CLKCTRL_IDLEST 0x00030000
#define CM_PER_GPIO1_CLKCTRL 0xAC
/*===========================================================================*/
@@ -344,6 +347,13 @@
#define CONF_GPMC_A6 0x0858
#define CONF_GPMC_A7 0x085c
#define CONF_GPMC_A8 0x0860
+#define CONF_MMC0_DAT3 0x08F0
+#define CONF_MMC0_DAT2 0x08F4
+#define CONF_MMC0_DAT1 0x08F8
+#define CONF_MMC0_DAT0 0x08FC
+#define CONF_MMC0_CLK 0x0900
+#define CONF_MMC0_CMD 0x0904
+#define CONF_SPI0_CS1 0x0960
#define CONF_UART0_RXD 0x0970
#define CONF_UART0_TXD 0x0974
#define DDR_IO_CTRL 0x0E04
@@ -456,9 +466,6 @@
/* DMTimer7 Registers */
#define DMTIMER7_BASE (L4_PER_BASE + 0x0004A000)
#define DMTIMER7_REG(_x_) *(vulong *)(DMTIMER7_BASE + _x_)
-/* MMCHS0 Registers */
-#define MMCHS0_BASE (L4_PER_BASE + 0x00060000)
-#define MMCHS0_REG(_x_) *(vulong *)(MMCHS0_BASE + _x_)
/* ELM Registers */
#define ELM_BASE (L4_PER_BASE + 0x00080000)
#define ELM_REG(_x_) *(vulong *)(ELM_BASE + _x_)
@@ -1221,7 +1228,10 @@
/*===========================================================================*/
/* MMC */
/*===========================================================================*/
-/* MMC Registers offset */
+/* MMCHS0 Registers base */
+#define MMCHS0_BASE (L4_PER_BASE + 0x00060000)
+#define MMCHS0_REG(_x_) *(vulong *)(MMCHS0_BASE + _x_)
+/* MMC Registers base */
#define MMC1_BASE (L4_PER_BASE + 0x001D8000)
#define MMC1_REG(_x_) *(vulong *)(MMC1_BASE + _x_)
/*---------------------------------------------------------------------------*/
@@ -1229,26 +1239,181 @@
/* System Configuration */
#define SD_SYSCONFIG 0x0110
+#define SD_SYSCONFIG_CLOCKACTIVITY 0x00000300
+#define SD_SYSCONFIG_SIDLEMODE 0x00000018
+#define SD_SYSCONFIG_SIDLEMODE_IDLE 0x00000000
+#define SD_SYSCONFIG_SIDLEMODE_IGNORE 0x00000008
+#define SD_SYSCONFIG_SIDLEMODE_WKUP 0x00000010
+#define SD_SYSCONFIG_ENAWAKEUP 0x00000004
+#define SD_SYSCONFIG_ENAWAKEUP_DISABLE 0x00000000
+#define SD_SYSCONFIG_ENAWAKEUP_ENABLE 0x00000004
+#define SD_SYSCONFIG_SOFTRESET 0x00000002
+#define SD_SYSCONFIG_AUTOIDLE 0x00000001
+#define SD_SYSCONFIG_AUTOIDLE_AUTOGATE 0x00000001
/* System Status */
#define SD_SYSSTATUS 0x0114
+#define SD_SYSSTATUS_RESETDONE 0x00000001
/* Card Status Response Error */
#define SD_CSRE 0x0124
/* System Test */
#define SD_SYSTEST 0x0128
/* Configuration */
#define SD_CON 0x012C
+#define SD_CON_SDMA_LNE 0x00200000
+#define SD_CON_DMA_MNS 0x00100000
+#define SD_CON_DDR 0x00080000
+#define SD_CON_BOOT_CF0 0x00040000
+#define SD_CON_BOOT_ACK 0x00020000
+#define SD_CON_CLKEXTFREE 0x00010000
+#define SD_CON_PADEN 0x00008000
+#define SD_CON_CEATA 0x00001000
+#define SD_CON_CTPL 0x00000800
+#define SD_CON_DVAL 0x00000600
+#define SD_CON_DVAL_33US 0x00000000
+#define SD_CON_DVAL_231US 0x00000200
+#define SD_CON_DVAL_1MS 0x00000400
+#define SD_CON_DVAL_840US 0x00000600
+#define SD_CON_WPP 0x00000100
+#define SD_CON_CDP 0x00000080
+#define SD_CON_CDP_ACTIVE_LOW 0x00000080
+#define SD_CON_CDP_ACTIVE_HIGH 0x00000000
+#define SD_CON_MIT 0x00000040
+#define SD_CON_DW8 0x00000020
+#define SD_CON_DW8_1BIT_OR_4BIT 0x00000000
+#define SD_CON_DW8_8BIT 0x00000020
+#define SD_CON_MODE 0x00000010
+#define SD_CON_MODE_SYSTEST 0x00000010
+#define SD_CON_MODE_NORMAL 0x00000000
+#define SD_CON_STR 0x00000008
+#define SD_CON_HR 0x00000004
+#define SD_CON_INIT 0x00000002
+#define SD_CON_INIT_START 0x00000002
+#define SD_CON_INIT_END 0x00000000
+#define SD_CON_OD 0x00000001
+#define SD_CON_OD_ENABLE 0x00000001
+#define SD_CON_OD_DISABLE 0x00000000
/* Power Counter */
#define SD_PWCNT 0x0130
/* SDMA System Address */
#define SD_SDMASA 0x0200
/* Transfer Length Configuration */
#define SD_BLK 0x0204
+#define SD_BLK_512_BYTES 0x00000200
/* Command Argument */
#define SD_ARG 0x0208
/* Command and Transfer Mode */
#define SD_CMD 0x020C
+#define SD_CMD_CMD0_GO_IDLE_STATE 0x00000000
+#define SD_CMD_CMD0_GO_PRE_IDLE_STATE 0x00000000
+#define SD_CMD_CMD0_BOOT_INITIATION 0x00000000
+#define SD_CMD_CMD1_SEND_OP_COND 0x01000000
+#define SD_CMD_CMD2_ALL_SEND_CID 0x02000000
+#define SD_CMD_CMD3_SEND_RELATIVE_ADDR 0x03000000
+#define SD_CMD_CMD3_SET_RELATIVE_ADDR 0x03000000
+#define SD_CMD_CMD4_SET_DSR 0x04000000
+#define SD_CMD_CMD5_SLEEP_AWAKE 0x05000000
+#define SD_CMD_CMD6_SWITCH_FUNC 0x06000000
+#define SD_CMD_CMD6_SWITCH 0x06000000
+#define SD_CMD_CMD7_SELECT_DESELECT_CARD 0x07000000
+#define SD_CMD_CMD8_SEND_IF_COND 0x08000000
+#define SD_CMD_CMD8_SEND_EXT_CSD 0x08000000
+#define SD_CMD_CMD9_SEND_CSD 0x09000000
+#define SD_CMD_CMD10_SEND_CID 0x0A000000
+#define SD_CMD_CMD11_READ_DAT 0x0B000000
+#define SD_CMD_CMD12_STOP_TRANSMISSION 0x0C000000
+#define SD_CMD_CMD13_SEND_STATUS 0x0D000000
+#define SD_CMD_CMD14_BUSTEST_R 0x0E000000
+#define SD_CMD_CMD15_GO_INACTIVE_STATE 0x0F000000
+#define SD_CMD_CMD16_SET_BLOCKLEN 0x10000000
+#define SD_CMD_CMD17_READ_SINGLE_BLOCK 0x11000000
+#define SD_CMD_CMD18_READ_MULTIPLE_BLOCK 0x12000000
+#define SD_CMD_CMD19_BUSTEST_W 0x13000000
+#define SD_CMD_CMD20_WRITE_DAT_UNTIL_STOP 0x14000000
+#define SD_CMD_CMD24_WRITE_BLOCK 0x18000000
+#define SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK 0x19000000
+#define SD_CMD_CMD26_PROGRAM_CID 0x1A000000
+#define SD_CMD_CMD27_PROGRAM_CSD 0x1B000000
+#define SD_CMD_CMD28_SET_WRITE_PROT 0x1C000000
+#define SD_CMD_CMD29_CLR_WRITE_PROT 0x1D000000
+#define SD_CMD_CMD30_SEND_WRITE_PROT 0x1E000000
+#define SD_CMD_CMD31_SEND_WRITE_PROT_TYPE 0x1F000000
+#define SD_CMD_CMD32_ERASE_WR_BLK_START 0x20000000
+#define SD_CMD_CMD33_ERASE_WR_BLK_END 0x21000000
+#define SD_CMD_CMD35_ERASE_GROUP_START 0x23000000
+#define SD_CMD_CMD36_ERASE_GROUP_END 0x24000000
+#define SD_CMD_CMD38_ERASE 0x26000000
+#define SD_CMD_CMD39_FAST_IO 0x27000000
+#define SD_CMD_CMD40_GO_IRQ_STATE 0x28000000
+#define SD_CMD_CMD42_LOCK_UNLOCK 0x2A000000
+#define SD_CMD_CMD55_APP_CMD 0x37000000
+#define SD_CMD_CMD56_GEN_CMD 0x38000000
+
+#define SD_CMD_ACMD6_SET_BUS_WIDTH 0x06000000
+#define SD_CMD_ACMD13_SD_STATUS 0x0D000000
+#define SD_CMD_ACMD22_SEND_NUM_WR_BLOCKS 0x16000000
+#define SD_CMD_ACMD23_SET_WR_BLK_ERASE_COUNT 0x17000000
+#define SD_CMD_ACMD41_SD_SEND_OP_COND 0x29000000
+#define SD_CMD_ACMD42_SET_CLR_CARD_DETECT 0x2A000000
+#define SD_CMD_ACMD51_SEND_SCR 0x33000000
+
+#define SD_CMD_CMD_TYPE_NORMAL 0x00000000
+#define SD_CMD_CMD_TYPE_SUSPEND 0x00400000
+#define SD_CMD_CMD_TYPE_RESUME 0x00800000
+#define SD_CMD_CMD_TYPE_ABORT 0x00C00000
+
+#define SD_CMD_DP_NO_DATA_PRESENT 0x00000000
+#define SD_CMD_DP_DATA_PRESENT 0x00200000
+
+#define SD_CMD_CICE_DISABLE 0x00000000
+#define SD_CMD_CICE_ENABLE 0x00100000
+
+#define SD_CMD_CCCE_DISABLE 0x00000000
+#define SD_CMD_CCCE_ENABLE 0x00080000
+
+#define RSP_TYPE_NO_RESPONSE 0x00000000
+#define RSP_TYPE_136 0x00010000
+#define RSP_TYPE_48 0x00020000
+#define RSP_TYPE_48_WITH_BUSY 0x00030000
+#define SD_CMD_RSP_TYPE_NO_RESPONSE RSP_TYPE_NO_RESPONSE
+#define SD_CMD_RSP_TYPE_R1 RSP_TYPE_48
+#define SD_CMD_RSP_TYPE_R1B RSP_TYPE_48_WITH_BUSY
+#define SD_CMD_RSP_TYPE_R2 RSP_TYPE_136
+#define SD_CMD_RSP_TYPE_R3 RSP_TYPE_48
+#define SD_CMD_RSP_TYPE_R4 RSP_TYPE_48
+#define SD_CMD_RSP_TYPE_R5 RSP_TYPE_48
+#define SD_CMD_RSP_TYPE_R5B RSP_TYPE_48_WITH_BUSY
+#define SD_CMD_RSP_TYPE_R6 RSP_TYPE_48
+#define SD_CMD_RSP_TYPE_R7 RSP_TYPE_48
+
+#define SD_CMD_MSBS_SINGLE 0x00000000
+#define SD_CMD_MSBS_MULTIPLE 0x00000020
+
+#define SD_CMD_DDIR_WRITE 0x00000000
+#define SD_CMD_DDIR_READ 0x00000010
+
+#define SD_CMD_ACEN_DISABLE 0x00000000
+#define SD_CMD_ACEN_CMD12_ENABLE 0x00000004
+
+#define SD_CMD_BCE_DISABLE 0x00000000
+#define SD_CMD_BCE_ENABLE 0x00000002
+
+#define SD_CMD_DE_DISABLE 0x00000000
+#define SD_CMD_DE_ENABLE 0x00000001
+
/* Command Response 0 and 1 */
#define SD_RSP10 0x0210
+#define SD_RSP10_R1_CURRENT_STATE 0x00001E00
+#define SD_RSP10_R1_CURRENT_STATE_IDLE 0x00000000
+#define SD_RSP10_R1_CURRENT_STATE_READY 0x00000200
+#define SD_RSP10_R1_CURRENT_STATE_IDENTIFICATION 0x00000400
+#define SD_RSP10_R1_CURRENT_STATE_STANDBY 0x00000600
+#define SD_RSP10_R1_CURRENT_STATE_TRANSFER 0x00000800
+#define SD_RSP10_R1_CURRENT_STATE_SENDING_DATA 0x00000A00
+#define SD_RSP10_R1_CURRENT_STATE_RECEIVE_DATA 0x00000C00
+#define SD_RSP10_R1_CURRENT_STATE_PROGRAMMING 0x00000E00
+#define SD_RSP10_R1_CURRENT_STATE_DISCONNECT 0x00001000
+#define SD_RSP10_R3_CARD_CAPACITY_STATUS 0x40000000
+#define SD_RSP10_R3_CARD_POWER_UP_STATUS 0x80000000
/* Command Response 2 and 3 */
#define SD_RSP32 0x0214
/* Command Response 4 and 5 */
@@ -1259,20 +1424,103 @@
#define SD_DATA 0x0220
/* Present State */
#define SD_PSTATE 0x0224
+#define SD_PSTATE_CLEV 0x01000000
+#define SD_PSTATE_DLEV 0x00F00000
+#define SD_PSTATE_WP 0x00080000
+#define SD_PSTATE_CDPL 0x00040000
+#define SD_PSTATE_CSS 0x00020000
+#define SD_PSTATE_CINS 0x00010000
+#define SD_PSTATE_BRE 0x00000800
+#define SD_PSTATE_BWE 0x00000400
+#define SD_PSTATE_RTA 0x00000200
+#define SD_PSTATE_WTA 0x00000100
+#define SD_PSTATE_DLA 0x00000004
+#define SD_PSTATE_DATI 0x00000002
+#define SD_PSTATE_CMDI 0x00000001
/* Host Control */
#define SD_HCTL 0x0228
+#define SD_HCTL_SDVS 0x00000E00
+#define SD_HCTL_SDVS_VS18 0x00000A00
+#define SD_HCTL_SDVS_VS30 0x00000C00
+#define SD_HCTL_SDVS_VS33 0x00000E00
+#define SD_HCTL_SDBP 0x00000100
+#define SD_HCTL_DMAS 0x00000180
+#define SD_HCTL_DMAS_32BIT_ADDR_ADMA2 0x00000010
+#define SD_HCTL_DTW 0x00000002
+#define SD_HCTL_DTW_1BIT 0x00000000
+#define SD_HCTL_DTW_4BIT 0x00000002
/* SD System Control */
#define SD_SYSCTL 0x022C
+#define SD_SYSCTL_SRC 0x02000000
+#define SD_SYSCTL_SRA 0x01000000
+#define SD_SYSCTL_DTO 0x000F0000
+#define SD_SYSCTL_DTO_TCF_2_13 0x00000000
+#define SD_SYSCTL_DTO_TCF_2_14 0x00010000
+#define SD_SYSCTL_DTO_TCF_2_27 0x000E0000
+#define SD_SYSCTL_CLKD 0x0000FFC0
+#define SD_SYSCTL_CEN 0x00000004
+#define SD_SYSCTL_CEN_ENABLE 0x00000004
+#define SD_SYSCTL_ICS 0x00000002
+#define SD_SYSCTL_ICE 0x00000001
+#define SD_SYSCTL_ICE_ENABLE 0x00000001
/* SD Interrupt Status */
#define SD_STAT 0x0230
+#define SD_STAT_BADA 0x20000000
+#define SD_STAT_CERR 0x10000000
+#define SD_STAT_ADMAE 0x02000000
+#define SD_STAT_ACE 0x01000000
+#define SD_STAT_DEB 0x00400000
+#define SD_STAT_DCRC 0x00200000
+#define SD_STAT_DTO 0x00100000
+#define SD_STAT_CIE 0x00080000
+#define SD_STAT_CEB 0x00040000
+#define SD_STAT_CCRC 0x00020000
+#define SD_STAT_CTO 0x00010000
+#define SD_STAT_ERRI 0x00008000
+#define SD_STAT_BSR 0x00000400
+#define SD_STAT_OBI 0x00000200
+#define SD_STAT_CIRQ 0x00000100
+#define SD_STAT_CREM 0x00000080
+#define SD_STAT_CINS 0x00000040
+#define SD_STAT_BRR 0x00000020
+#define SD_STAT_BWR 0x00000010
+#define SD_STAT_DMA 0x00000008
+#define SD_STAT_BGE 0x00000004
+#define SD_STAT_TC 0x00000002
+#define SD_STAT_CC 0x00000001
/* SD Interrupt Enable */
#define SD_IE 0x0234
+#define SD_IE_BADA_ENABLE 0x20000000
+#define SD_IE_CERR_ENABLE 0x10000000
+#define SD_IE_ADMA_ENABLE 0x02000000
+#define SD_IE_ACE_ENABLE 0x01000000
+#define SD_IE_DEB_ENABLE 0x00400000
+#define SD_IE_DCRC_ENABLE 0x00200000
+#define SD_IE_DTO_ENABLE 0x00100000
+#define SD_IE_CIE_ENABLE 0x00080000
+#define SD_IE_CEB_ENABLE 0x00040000
+#define SD_IE_CCRC_ENABLE 0x00020000
+#define SD_IE_CTO_ENABLE 0x00010000
+#define SD_IE_BSR_ENABLE 0x00000400
+#define SD_IE_OBI_ENABLE 0x00000200
+#define SD_IE_CIRQ_ENABLE 0x00000100
+#define SD_IE_CREM_ENABLE 0x00000080
+#define SD_IE_CINS_ENABLE 0x00000040
+#define SD_IE_BRR_ENABLE 0x00000020
+#define SD_IE_BWR_ENABLE 0x00000010
+#define SD_IE_DMA_ENABLE 0x00000008
+#define SD_IE_BGE_ENABLE 0x00000004
+#define SD_IE_TC_ENABLE 0x00000002
+#define SD_IE_CC_ENABLE 0x00000001
/* SD Interrupt Enable Set */
#define SD_ISE 0x0238
/* Auto CMD12 Error Status */
#define SD_AC12 0x023C
/* Capabilities */
#define SD_CAPA 0x0240
+#define SD_CAPA_VS18 0x04000000
+#define SD_CAPA_VS30 0x02000000
+#define SD_CAPA_VS33 0x01000000
/* Maximum Current Capabilities */
#define SD_CUR_CAPA 0x0148
/* Force Event */
--
2.5.0
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