[PATCH 2/6] BBB: cpuio.c: Configure pins used for MMC0 interface
Jarielle Catbagan
jcatbagan93 at gmail.com
Mon Aug 3 04:16:39 UTC 2015
---
ports/beagleboneblack/cpuio.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/ports/beagleboneblack/cpuio.c b/ports/beagleboneblack/cpuio.c
index 301a065..eab0a00 100644
--- a/ports/beagleboneblack/cpuio.c
+++ b/ports/beagleboneblack/cpuio.c
@@ -157,6 +157,22 @@ pinMuxInit(void)
// GPIO1_24: USER3 LED (D5)
CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON |
PULL_OFF | MUXMODE_7;
+
+ // Configure the pins for the MMC0 interface
+ CNTL_MODULE_REG(CONF_MMC0_DAT0) = RX_ON | PULL_ON |
+ PULLUP | MUXMODE_0;
+ CNTL_MODULE_REG(CONF_MMC0_DAT1) = RX_ON | PULL_ON |
+ PULLUP | MUXMODE_0;
+ CNTL_MODULE_REG(CONF_MMC0_DAT2) = RX_ON | PULL_ON |
+ PULLUP | MUXMODE_0;
+ CNTL_MODULE_REG(CONF_MMC0_DAT3) = RX_ON | PULL_ON |
+ PULLUP | MUXMODE_0;
+ CNTL_MODULE_REG(CONF_MMC0_CLK) = RX_ON | PULL_OFF |
+ MUXMODE_0;
+ CNTL_MODULE_REG(CONF_MMC0_CMD) = RX_ON | PULL_ON |
+ PULLUP | MUXMODE_0;
+ CNTL_MODULE_REG(CONF_SPI0_CS1) = RX_ON | PULL_ON |
+ PULLUP | MUXMODE_5;
}
void
--
2.5.0
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