[PATCH 10/16] Basic Umon image for UART booting

Jarielle Catbagan jcatbagan93 at gmail.com
Wed Jun 17 18:16:51 UTC 2015


Added a method to print a character in a loop via UART for the
Beaglebone Black for debugging purposes.  Changed ALLOCSIZE and
MONSTACKSIZE to 1K and set all INCLUDE_xx defines to 0.  Replaced the
csb740-specific cpu.h with the template version.  Replaced the cpuio.h
with the template version while retaining the implementation  for
getUartDivisor() since an external definition is required by
uart16550.c.  Removed Cogent setup for csb740/omap3530 in rom_reset.S.
Jumping to target_putchar_loop instead of start for testing purposes.
Added a tempory implementation file to declare/define 'MonStack',
'adsHelp', and 'ads' in order to build a basic Umon image.

---
 main/dev/uart16550.c              |   7 +
 main/dev/uart16550.h              |   1 +
 ports/beagleboneblack/Makefile    |  36 ++--
 ports/beagleboneblack/config.h    |  76 ++++-----
 ports/beagleboneblack/cpu.h       |  26 +--
 ports/beagleboneblack/cpuio.c     | 348 +++++++++-----------------------------
 ports/beagleboneblack/cpuio.h     |  77 +--------
 ports/beagleboneblack/rom_reset.S | 194 +--------------------
 8 files changed, 144 insertions(+), 621 deletions(-)

diff --git a/main/dev/uart16550.c b/main/dev/uart16550.c
index 0326d7a..decabd0 100644
--- a/main/dev/uart16550.c
+++ b/main/dev/uart16550.c
@@ -193,3 +193,10 @@ target_gotachar(void)
 #endif
  return(0);
 }
+
+void
+target_putchar_loop(void)
+{
+ while (1)
+ target_putchar('j');
+}
diff --git a/main/dev/uart16550.h b/main/dev/uart16550.h
index 3700445..b6712f6 100644
--- a/main/dev/uart16550.h
+++ b/main/dev/uart16550.h
@@ -132,6 +132,7 @@ extern int ConsoleBaudSet(int baud);
 extern int target_getchar(void);
 extern int target_gotachar(void);
 extern int target_putchar(char c);
+extern void target_putchar_loop(void);
 extern int target_console_empty(void);
 extern int getUartDivisor(int baud,unsigned char *hi, unsigned char *lo);

diff --git a/ports/beagleboneblack/Makefile b/ports/beagleboneblack/Makefile
index 73d6860..241c2e9 100644
--- a/ports/beagleboneblack/Makefile
+++ b/ports/beagleboneblack/Makefile
@@ -43,29 +43,21 @@ include $(TOPDIR)/make/common.make

 # Build each variable from a list of individual filenames...
 #
-LOCSSRC =
+LOCSSRC =
 CPUSSRC = vectors_arm.S
-LOCCSRC =
-COMCSRC =
-CPUCSRC =
-IODEVSRC =
-FLASHSRC =
-#LOCSSRC =
-#CPUSSRC = vectors_arm.S
-#LOCCSRC = cpuio.c etherdev.c nand740.c omap3530_gpio.c \
-#  omap3530_lcd.c omap3530_sdmmc.c
-#COMCSRC = arp.c cast.c cache.c chario.c cmdtbl.c \
-#  docmd.c dhcp_00.c dhcpboot.c dns.c edit.c env.c ethernet.c \
-#  flash.c gdb.c icmp.c if.c ledit_vt100.c monprof.c \
-#  fbi.c font.c mprintf.c memcmds.c malloc.c moncom.c memtrace.c \
-#  misccmds.c misc.c nand.c password.c redirect.c \
-#  reg_cache.c sbrk.c sd.c \
-#  start.c struct.c symtbl.c syslog.c tcpstuff.c tfs.c tfsapi.c \
-#  tfsclean1.c tfscli.c tfsloader.c tfslog.c tftp.c timestuff.c \
-#  tsi.c xmodem.c
-#CPUCSRC = ldatags.c except_arm.c misc_arm.c strace_arm.c
-#IODEVSRC = smsc911x.c uart16550.c fb_draw.c
-#FLASHSRC = s29gl512n_16x1.c
+LOCCSRC = cpuio.c test.c
+COMCSRC = arp.c cast.c cache.c chario.c cmdtbl.c \
+  docmd.c dhcp_00.c dhcpboot.c dns.c edit.c env.c ethernet.c \
+  flash.c gdb.c icmp.c if.c ledit_vt100.c monprof.c \
+  fbi.c font.c mprintf.c memcmds.c malloc.c moncom.c memtrace.c \
+  misccmds.c misc.c nand.c password.c redirect.c \
+  reg_cache.c sbrk.c sd.c \
+  start.c struct.c symtbl.c syslog.c tcpstuff.c tfs.c tfsapi.c \
+  tfsclean1.c tfscli.c tfsloader.c tfslog.c tftp.c timestuff.c \
+  tsi.c xmodem.c
+CPUCSRC = ldatags.c except_arm.c misc_arm.c strace_arm.c
+IODEVSRC = smsc911x.c uart16550.c fb_draw.c
+FLASHSRC = s29gl512n_16x1.c


 include $(TOPDIR)/make/objects.make
diff --git a/ports/beagleboneblack/config.h b/ports/beagleboneblack/config.h
index 432a41e..c4f9ab3 100644
--- a/ports/beagleboneblack/config.h
+++ b/ports/beagleboneblack/config.h
@@ -141,58 +141,58 @@
  * allocated to malloc in the monitor.  Note that this size can be dynamically
  * increased using the heap extension option in the heap command.
  */
-#define ALLOCSIZE (64*1024)
-#define MONSTACKSIZE (16*1024)
+#define ALLOCSIZE 1024 // (64*1024)
+#define MONSTACKSIZE 1024 // (16*1024)

 // Cogent specific options
 #define INCLUDE_I2C 0
-#define INCLUDE_LCD 1
+#define INCLUDE_LCD 0

 /* Specify inclusion of subsystems within the monitor here.
  * Refer to comments in common/monitor/inc_check.h for details on
  * each of these macros.
  */

-#define INCLUDE_MEMTRACE 1
-#define INCLUDE_MEMCMDS         1
-#define INCLUDE_EDIT            1
+#define INCLUDE_MEMTRACE 0
+#define INCLUDE_MEMCMDS         0
+#define INCLUDE_EDIT            0
 #define INCLUDE_DISASSEMBLER    0
-#define INCLUDE_UNZIP           1
-#define INCLUDE_ETHERNET        1
-#define INCLUDE_ICMP 1
-#define INCLUDE_TFTP            1
-#define INCLUDE_DHCPBOOT        1
-#define INCLUDE_TFS             1
-#define INCLUDE_TFSCLI          1
-#define INCLUDE_TFSAPI          1
-#define INCLUDE_TFSSCRIPT       1
-#define INCLUDE_TFSSYMTBL       1
-#define INCLUDE_XMODEM          1
-#define INCLUDE_LINEEDIT        1
+#define INCLUDE_UNZIP           0
+#define INCLUDE_ETHERNET        0
+#define INCLUDE_ICMP 0
+#define INCLUDE_TFTP            0
+#define INCLUDE_DHCPBOOT        0
+#define INCLUDE_TFS             0
+#define INCLUDE_TFSCLI          0
+#define INCLUDE_TFSAPI          0
+#define INCLUDE_TFSSCRIPT       0
+#define INCLUDE_TFSSYMTBL       0
+#define INCLUDE_XMODEM          0
+#define INCLUDE_LINEEDIT        0
 #define INCLUDE_EE              0
-#define INCLUDE_FLASH           1
-#define INCLUDE_STRACE          1
+#define INCLUDE_FLASH           0
+#define INCLUDE_STRACE          0
 #define INCLUDE_CAST            0
-#define INCLUDE_STRUCT          1
-#define INCLUDE_REDIRECT        1
-#define INCLUDE_QUICKMEMCPY     1
-#define INCLUDE_PROFILER        1
+#define INCLUDE_STRUCT          0
+#define INCLUDE_REDIRECT        0
+#define INCLUDE_QUICKMEMCPY     0
+#define INCLUDE_PROFILER        0
 #define INCLUDE_BBC             0
-#define INCLUDE_STOREMAC        1
-#define INCLUDE_SHELLVARS 1
-#define INCLUDE_MALLOC 1
+#define INCLUDE_STOREMAC        0
+#define INCLUDE_SHELLVARS 0
+#define INCLUDE_MALLOC 0
 #define INCLUDE_PORTCMD        0
-#define INCLUDE_SYSLOG        1
-#define INCLUDE_HWTMR        1
-#define INCLUDE_VERBOSEHELP     1
-#define INCLUDE_GDB    1
-#define INCLUDE_USRLVL 0
-#define INCLUDE_JFFS2 0
-#define INCLUDE_JFFS2ZLIB 0
-#define INCLUDE_FBI 1
-#define INCLUDE_TSI 1
-#define INCLUDE_SD 0
-#define INCLUDE_DNS 1
+#define INCLUDE_SYSLOG        0
+#define INCLUDE_HWTMR        0
+#define INCLUDE_VERBOSEHELP     0
+#define INCLUDE_GDB 0
+#define INCLUDE_USRLVL 0
+#define INCLUDE_JFFS2 0
+#define INCLUDE_JFFS2ZLIB 0
+#define INCLUDE_FBI 0
+#define INCLUDE_TSI 0
+#define INCLUDE_SD 0
+#define INCLUDE_DNS 0

 /* Inclusion of this next file will make sure that all of the above
  * inclusions are legal; and warn/adjust where necessary.
diff --git a/ports/beagleboneblack/cpu.h b/ports/beagleboneblack/cpu.h
index ddedd7b..9d17721 100644
--- a/ports/beagleboneblack/cpu.h
+++ b/ports/beagleboneblack/cpu.h
@@ -1,25 +1,3 @@
 /* cpu.h:
-    General notice:
-    This code is part of a boot-monitor package developed as a generic base
-    platform for embedded system designs.  As such, it is likely to be
-    distributed to various projects beyond the control of the original
-    author.  Please notify the author of any enhancements made or bugs found
-    so that all may benefit from the changes.  In addition, notification back
-    to the author will allow the new user to pick up changes that may have
-    been made by other users after this version of the code was distributed.
-
-    Author: Ed Sutter
-    email:  esutter at lucent.com
-    phone:  908-582-2351
-
-*/
-#include "omap3530.h"
-
-#define RESETMACRO() \
-{ \
- WD2_REG(WD_WCRR) = 0xfffffff0; \
- WD2_REG(WD_WSPR) = 0x0000bbbb; \
- while(*(volatile unsigned long *)(WD2_BASE_ADD + WD_WWPS)); \
- WD2_REG(WD_WSPR) = 0x00004444; \
- while(1); \
-}
+ */
+#define MONARGV0 "umon"
diff --git a/ports/beagleboneblack/cpuio.c b/ports/beagleboneblack/cpuio.c
index 0a9a262..8f2fbed 100644
--- a/ports/beagleboneblack/cpuio.c
+++ b/ports/beagleboneblack/cpuio.c
@@ -1,64 +1,11 @@
-//=============================================================================
-//
-//      cpuio.c
-//
-//      CPU/Board Specific IO
-//
-// Author(s):    Luis Torrico, Cogent Computer Systems, Inc.
-// Date:         12/04/2008
-// Description:  This file contains the IO functions required by Micro Monitor
-// that are unique to the CSB740
-//
-//
-//=============================================================================
-
 #include "config.h"
+#include "stddefs.h"
 #include "cpuio.h"
 #include "genlib.h"
-#include "ether.h"
-#include "stddefs.h"
+#include "cache.h"
 #include "warmstart.h"
-#include "omap3530.h"
-#include "omap3530_mem.h"
-#include "cpu_gpio.h"
-#include "fb_draw.h"
-#include "uart16550.h"
-#include "umongpio.h"
-#include "ad7843.h"
-
-#define __raw_readl(a)    (*(volatile unsigned int *)(a))
-
-extern ulong i2c_init(void);
-extern ulong getpsr(void);
-extern void putpsr(ulong);
-
-uchar bcolor=0; // vga black
-
-/******************************************************
-// Delay for some usecs. - Not accurate, assumes ROM mode
-// and no Cache
- ******************************************************/
-void udelay(int delay)
-{
-  volatile int i;
-  for ( i = LOOPS_PER_USEC * delay; i ; i--);
-}
+#include "timer.h"

-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base + WD_WWPS);
- } while (pending);
-}
-
-/******************************************************
-// getUARTDivisor is called from UART16550.c
- ******************************************************/
 int
 getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
 {
@@ -67,247 +14,106 @@ getUartDivisor(int baud, unsigned char *hi,
unsigned char *lo)
  return(0);
 }

-/******************************************************
-// Set pads (pins) to correct mode.  Refer to section 7.4.4
- in TI omap35xx_tech_ref_manual for bit defines.
- ******************************************************/
-void pads_init()
-{
- // Set up chip selects
- SCM_REG(PADCONFS_GPMC_NCS3) = 0x00180018; // NCS3[15:0], NCS4[31:16]
- SCM_REG(PADCONFS_GPMC_NCS5) = 0x011C0018; // NCS5[15:0], EXP_INTX[31:16]
-
- // Set LCD_BKL_X to output, pullup enabled, mode 4
- // Set LCLK to output, no pull-type and disabled, mode 0
- SCM_REG(PADCONFS_GPMC_NCS7) = 0x0000001C; // LCD_BKL_X[15:0],
LCLK(or GPIO_59)[31:16]
-
- // Set LCD pads to outputs, pull-type = up, pullud disabled, mode 0
- SCM_REG(PADCONFS_DSS_PCLK) = 0x00100010; // LCD_PCLK_X[15:0], LCD_HS_X[31:16]
- SCM_REG(PADCONFS_DSS_VSYNC) = 0x00100010; // LCD_VS_X[15:0], LCD_OE_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA0) = 0x00100010; // LCD_B0_X[15:0], LCD_B1_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA2) = 0x00100010; // LCD_B2_X[15:0], LCD_B3_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA4) = 0x00100010; // LCD_B4_X[15:0], LCD_B5_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA6) = 0x00100010; // LCD_G0_X[15:0], LCD_G1_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA8) = 0x00100010; // LCD_G2_X[15:0], LCD_G3_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA10) = 0x00100010; // LCD_G4_X[15:0], LCD_G5_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA12) = 0x00100010; // LCD_R0_X[15:0], LCD_R1_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA14) = 0x00100010; // LCD_R2_X[15:0], LCD_R3_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA16) = 0x00100010; // LCD_R4_X[15:0], LCD_R5_X[31:16]
-
- // Set D_TXD for output and D_RXD for input.  Set both to pullup
enabled and mode 1
- SCM_REG(PADCONFS_MCBSP3_CLKX) = 0x01190019; // D_TXD[15:0], D_RXD[31:16]
-
-#ifdef AD7843_GPIOMODE
- // Depending on AD7843_GPIOMODE setting, we either configure the SPI
- // interface to the AD7843 as a real SPI device using the OMAP's SPI
- // controller, or we set it up with GPIO bits...
- SCM_REG(PADCONFS_DSS_DATA18) = 0x00040004;
- SCM_REG(PADCONFS_DSS_DATA20) = 0x00040104;
-#else
- SCM_REG(PADCONFS_DSS_DATA18) = 0x0002011A; // SPI1_CLK_X[15:0],
SPI1_MOSI_X[31:16]
- SCM_REG(PADCONFS_DSS_DATA20) = 0x001A011A; // SPI1_MISO_X[15:0],
*SPI1_CS0_X[31:16]
-#endif
-
- // Set PIRQ for ADS7843 touch interrupt.  Set both to pullup enabled
and mode 4
- SCM_REG(PADCONFS_MMC1_DAT4) = 0x01040104; // *I2C_INT_X[15:0], *PIRQ_X[31:16]
-
- // GPIO1 is the push button on CSB703(set as input), GPIO0 is is LED
on CSB703(set as output)
- SCM_REG(PADCONFS_MMC1_DAT6) = 0x01040004; // GPIO0_X[15:0], GPIO1_X[31:16]
-
- // Set E_INT* to be an input in GPIO mode
- SCM_REG(PADCONFS_GPMC_WAIT2) = 0x011C011f; // NA[15:0], E_INTX[31:16]
-
-   // Set SYS_CLKOUT1 for USB_CLK
-   SCM_REG(PADCONFS_SYS_OFF_MODE) = 0x0000010f;   //
OFF_MODE_X[15:0], SYS_CLKOUT1[31:16]
-
-   // Set SYS_CLKOUT2 for debug purposes
-   SCM_REG(PADCONFS_SYS_NIRQ) = 0x0000011f;   // FIQ[15:0], SYS_CLK2[31:16]
-
-}
-
-int
+/* devInit():
+ * As a bare minimum, initialize the console UART here using the
+ * incoming 'baud' value as the baud rate.
+ */
+void
 devInit(int baud)
 {
- // Initialize pads
-    pads_init();
-
- // Disable MPU Watchdog WDT2
- WD2_REG(WD_WSPR) = 0x0000aaaa;
- wait_for_command_complete(WD2_BASE_ADD);
- WD2_REG(WD_WSPR) = 0x00005555;
-
- // Initialize GPIO
- GPIO_init();
-
- // Setup UART pins to UART mode before calling InitUART from uart16550.c
- UART2_REG(UART_MDR1) = 0x0000;
-    // Initialize the UART
-    InitUART(baud);
-
- // Setup CS0 for 110ns Spansion Flash
- GPMC_REG(GPMC_CS0_CONFIG7) = 0x00000c48; // Base addr 0x08000000, 64M
- GPMC_REG(GPMC_CS0_CONFIG1) = 0x00001210;
- //GPMC_REG(GPMC_CS0_CONFIG5) = 0x00080808; // Config5
-
- // Setup CS4 for LAN9211, on the CSB740 it is refered to as CS2
- // and mapped to E_CS
- GPMC_REG(GPMC_CS4_CONFIG7) = 0x00000F6C; // Base addr 0x2C000000, 16M
- GPMC_REG(GPMC_CS4_CONFIG1) = 0x00001200;
-
- return 0;
+ /* ADD_CODE_HERE */
 }

-/* Referring to table 25-10 of the TRM, install
- * the RAM exception vectors...
+/* ConsoleBaudSet():
+ * Provide a means to change the baud rate of the running
+ * console interface.  If the incoming value is not a valid
+ * baud rate, then default to 9600.
+ * In the early stages of a new port this can be left empty.
+ * Return 0 if successful; else -1.
  */
-void
-ram_vector_install(void)
+/*int
+ConsoleBaudSet(int baud)
 {
- extern unsigned long abort_data;
- extern unsigned long abort_prefetch;
- extern unsigned long undefined_instruction;
- extern unsigned long software_interrupt;
- extern unsigned long interrupt_request;
- extern unsigned long fast_interrupt_request;
- extern unsigned long not_assigned;
-
- *(ulong **)0x4020ffe4 = &undefined_instruction;
- *(ulong **)0x4020ffe8 = &software_interrupt;
- *(ulong **)0x4020ffec = &abort_prefetch;
- *(ulong **)0x4020fff0 = &abort_data;
- *(ulong **)0x4020fff4 = &not_assigned;
- *(ulong **)0x4020fff8 = &interrupt_request;
- *(ulong **)0x4020fffc = &fast_interrupt_request;
-}
-
-void
-initCPUio()
+ // ADD_CODE_HERE
+ return(0);
+}*/
+
+/* target_console_empty():
+ * Target-specific portion of flush_console() in chario.c.
+ * This function returns 1 if there are no characters waiting to
+ * be put out on the UART; else return 0 indicating that the UART
+ * is still busy outputting characters from its FIFO.
+ * In the early stages of a new port this can simply return 1.
+ */
+/*int
+target_console_empty(void)
 {
- volatile unsigned register cntens;
- volatile unsigned register usren;
- volatile unsigned register pmnc;
-
- ram_vector_install();
-
- /* Do this stuff to enable the cycle counter
- * (for use by target_timer)...
- */
- /* Allow user mode to have access to performance monitor registers:
- */
-   asm volatile ("   MRC p15, 0, %0, c9, c14, 0" : "=r" (usren));
- usren |= 1;
-   asm volatile ("   MCR p15, 0, %0, c9, c14, 0" : : "r" (usren));
-
- /* Enable all counters, and reset Cycle counter...
- */
- asm volatile ("   MRC p15, 0, %0, c9, c12, 0" : "=r" (pmnc));
- pmnc |= 5;
- asm volatile ("   MCR p15, 0, %0, c9, c12, 0" : : "r" (pmnc));
-
- /* Enable all performance counter registers...
- */
- asm volatile ("   MRC p15, 0, %0, c9, c12, 1" : "=r" (cntens));
- cntens |= 0x8000000f;
- asm volatile ("   MCR p15, 0, %0, c9, c12, 1" : : "r" (cntens));
-}
-
-/* target_reset():
- * Set the counter to 16 ticks before trigger, then enable the
- * watchdog timer (WDT2) and wait...
+ // if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
+ return(0);
+ return(1);
+}*/
+
+/* intsoff():
+ * Disable all system interrupts here and return a value that can
+ * be used by intsrestore() (later) to restore the interrupt state.
  */
-void
-target_reset(void)
+ulong
+intsoff(void)
 {
- // Preload the count-up register...
- WD2_REG(WD_WCRR) = 0xfffffff0;
-
- // Start MPU Watchdog WDT2
- WD2_REG(WD_WSPR) = 0x0000bbbb;
- wait_for_command_complete(WD2_BASE_ADD);
- WD2_REG(WD_WSPR) = 0x00004444;
+ ulong status;

- // Now just wait...
- while(1);
+ /* ADD_CODE_HERE */
+ return(status);
 }

+/* intsrestore():
+ * Re-establish system interrupts here by using the status value
+ * that was returned by an earlier call to intsoff().
+ */
 void
-intsrestore(psr)
-ulong     psr;
+intsrestore(ulong status)
 {
-    putpsr(psr);
+ /* ADD_CODE_HERE */
 }

-/*
- * Read the program status register (CPSR)
- * and set the FIQ and IRQ bits.
+/* cacheInitForTarget():
+ * Establish target specific function pointers and
+ * enable i-cache...
+ * Refer to $core/cache.c for a description of the function pointers.
+ * NOTE:
+ * If cache (either I or D or both) is enabled, then it is important
+ * that the appropriate cacheflush/invalidate function be established.
+ * This is very important because programs (i.e. cpu instructions) are
+ * transferred to memory using data memory accesses and could
+ * potentially result in cache coherency problems.
  */
-ulong
-intsoff(void)
+void
+cacheInitForTarget(void)
 {
-    ulong  psr;
-
-    psr = getpsr();
-
-    /*
-     * Set bit 6, bit 7 to disable interrupts.
-     */
-    putpsr(psr | 0x000000c0);
-    return(psr);
+ /* ADD_CODE_HERE */
 }

-/* show_revision():
- * Called when the system banner is printed...
+/* target_reset():
+ * The default (absolute minimum) action to be taken by this function
+ * is to call monrestart(INITIALIZE).  It would be better if there was
+ * some target-specific function that would really cause the target
+ * to reset...
  */
 void
-show_revision(int center)
+target_reset(void)
 {
- int (*pfunc)(char *, ...);
- volatile unsigned register main_id;
- volatile unsigned register silicon_id;
-
- if (center)
- pfunc = cprintf;
- else
- pfunc = printf;
-
- asm("   MRC p15, 0, %0, c0, c0, 0" : "=r" (main_id));
- asm("   MRC p15, 1, %0, c0, c0, 7" : "=r" (silicon_id));
-
- pfunc("Silicon ID: %d.%d\n",
- ((silicon_id & 0xf0)>>4),(silicon_id & 0xf));
-
- pfunc("CPU Rev: %d, Variant: %d\n",
- main_id & 0xf,(main_id & 0x00f00000) >> 20);
-
- pfunc("CM Rev: %d.%d, PRM Rev: %d.%d\n",
- CM_REV_MAJ(),CM_REV_MIN(),PRM_REV_MAJ(),PRM_REV_MIN());
+// flushDcache(0,0);
+// disableDcache();
+// invalidateIcache(0,0);
+// disableIcache();
+ monrestart(INITIALIZE);
 }

-/* target_timer():
- * Used in conjunction with INCLUDE_HWTMR and TIMER_TICKS_PER_MSEC
- * to set up a hardware based time base.
+/* If any CPU IO wasn't initialized in reset.S, do it here...
+ * This just provides a "C-level" IO init opportunity.
  */
-unsigned long
-target_timer(void)
-{
- volatile unsigned register ccr;
-
-   asm("   MRC p15, 0, %0, c9, c13, 0" : "=r" (ccr));
-
- return(ccr);
-}
-
-/* cacheInitForTarget():
-    Enable instruction cache only...
-*/
 void
-cacheInitForTarget()
+initCPUio(void)
 {
-    asm("   MRC p15, 0, r0, c1, c0, 0");
-    asm("   ORR r0, r0, #0x1000");  /* bit 12 is ICACHE enable*/
-    asm("   MCR p15, 0, r0, c1, c0, 0");
-
-    /* Flush instruction cache */
-    asm("   MCR p15, 0, r0, c7, c5, 0");
+ /* ADD_CODE_HERE */
 }
-
diff --git a/ports/beagleboneblack/cpuio.h b/ports/beagleboneblack/cpuio.h
index 64ff49c..2021851 100644
--- a/ports/beagleboneblack/cpuio.h
+++ b/ports/beagleboneblack/cpuio.h
@@ -1,76 +1,3 @@
-//=============================================================================
-//
-//      cpuio.h
-//
-//      CPU/Board Specific IO
-//
-// Author(s):    Luis Torrico, Cogent Computer Systems, Inc.
-// Date:         05-16-2008
-// Description:  This file contains the IO functions required by Micro Monitor
-// that are unique to each CPU/Board combination
-//
-//
-// cpuio.h for the CSB740 OMAP3530 Cortex-A8
-//
-//=============================================================================
-
-// board specific defines for micro monitor
-#define DEFAULT_BAUD_RATE   38400
-#define MON_CPU_CLOCK       400000000
-
-#define LOOPS_PER_USEC 5
-
-#define BASE_OF_NAND 0x1000
-#define SIZE_OF_NAND 0x100000
-
-// SMSC LAN9211 Ethernet
-#define SMSC911X_BASE_ADDRESS 0x2C000000 // CS4 on OMAP3530 but we call it CS2
-
-// LCD Defines
-//
-// The LCD frame buffer is fixed at 0x80200000, which is 2Mbyte from the
-// beginning of SDRAM space.  Note that we access it 16-bits at a time.
-
-#define LCD_BUF_ADD 0x80200000
-#define LCD_BUF(_x_) *(vushort *)(LCD_BUF_ADD + _x_) // Frame Buffer
-#define USE_FONT8X8
-#define LCD_GET_PIXEL_ADD(_X_, _Y_) (((_Y_ * PIXELS_PER_ROW) + _X_)*2)
-
-// defines for the display geometry - OSD043TN24 480x272 TFT
-// (some of these defines are also used by uMon's frame buffer interface)
-#define PIXELS_PER_ROW 480 //
-#define PIXELS_PER_COL 272 //
-#define BITS_PER_PIXEL 16 //
-#define PIXFMT_IS_RGB565 1
-#define FBDEV_SETSTART fbdev_setstart
-#define FRAME_BUFFER_BASE_ADDR LCD_BUF_ADD
-#define LCD_H_WIDTH 41 // pulse width in pixels
-#define LCD_H_FRONT 2 // front porch (sync to enable)
-#define LCD_H_BACK 2 // back porch (enable to sync)
-#define LCD_V_WIDTH 10 // pulse width in lines
-#define LCD_V_FRONT 2 // front porch (sync to enable)
-#define LCD_V_BACK 2 // back porch (enable to sync)
-//#define LCD_PCD 2 // LCD PERCLK3 = 32Mhz/PCD +1 = Pixel Clock ~ 4Mhz
-
-#define TOP 1
-#define BOTTOM (PIXELS_PER_COL-1)
-#define LEFT 0
-#define RIGHT (PIXELS_PER_ROW-1)
-#define CENTER_X (PIXELS_PER_ROW/2)
-#define CENTER_Y (PIXELS_PER_COL/2)
-
-#define ROWS_PER_SCREEN 17
-#define COLS_PER_SCREEN 60
-
-#define LCD_BG_DEF 9
-#define LCD_FG_DEF 15
-
-#define LCD_FB_SIZE(_depth_) (((PIXELS_PER_COL * PIXELS_PER_ROW) *
_depth_) / 8)
-
-#define LCD_ROW_SIZE(_depth_) ((PIXELS_PER_ROW * _depth_) / 8)
-
-#define LCD_GET_ADD(_row_, _col_, _depth_) (((((_row_ *
PIXELS_PER_ROW) * FONT_HEIGHT) \
-  + (_col_ * FONT_WIDTH)) \
-  * _depth_) / 8)
-
+#define DEFAULT_BAUD_RATE 38400

+#define MONARGV0 "umon"
diff --git a/ports/beagleboneblack/rom_reset.S
b/ports/beagleboneblack/rom_reset.S
index 686296c..199cc87 100644
--- a/ports/beagleboneblack/rom_reset.S
+++ b/ports/beagleboneblack/rom_reset.S
@@ -56,6 +56,7 @@
 /*********************************************************************/

     .extern start
+    .extern target_putchar_loop

     .global reset
     .global coldstart
@@ -95,196 +96,6 @@ coldstart_1:

 // bl cache_init

-//----------------------------------------------------------
-// Start of Cogent Setup for CSB740 OMAP3530
-//----------------------------------------------------------
-
-init_pbias:
- ldr r2, =0x00000000 // set bias for sdio1
- ldr r1, =0x48002520
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x00000606 // set bias for sdio1
- ldr r1, =0x48002520
- str r2, [r1]
-
- bl delay_200
-init_clocks:
- ldr r2, =0x00000037 // Enable DPLL1 in lock mode
- ldr r1, =0x48004904
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x000A7115 // Set DPLL1 (MPU) M = 625, (N +1)= 21 + 1,
MPU_CLK = ~545MHz
- ldr r1, =0x48004940
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x099F1700 // Set DPLL3 (CORE) M = 415, (N +1)= 23 + 1,
CORE_CLK = ~332MHz
- ldr r1, =0x48004D40
- str r2, [r1]
-
- bl delay_200
-
- //ldr r2, =0x00000080 // Enable SYS_CLKOUT2 for debug purposes
- //ldr r1, =0x48004D70
- //str r2, [r1]
-
- //bl delay_200
-
- ldr r2, =0x43fffe00 // Turn on all available module clocks
- ldr r1, =0x48004a00
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x7ffffedb // Turn on all available peripheral clocks
- ldr r1, =0x48004a10
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x00006000 // enable auto clock for UART1 and UART2
- ldr r1, =0x48004a30
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x00000028 // enable WDT2 and GPIO 1 functional clock
- ldr r1, =0x48004c00
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x0000002c // enable WDT2, GPIO 1 interface and 32Ksync
(for Linux) clock
- ldr r1, =0x48004c10
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x0003E000 // enable GPIO 2-6 functional clocks
- ldr r1, =0x48005000
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x0003E000 // enable GPIO 2-6 interface clocks
- ldr r1, =0x48005010
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x00000003 // enable DSS1_ALWON_FCLK
- ldr r1, =0x48004e00
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x00000001 // enable DSS interface clock
- ldr r1, =0x48004e10
- str r2, [r1]
-
- bl delay_200
-
- ldr r2, =0x0000100A // Set CLKSEL_DSS1 to divide by 1
- ldr r1, =0x48004e40
- str r2, [r1]
-
- bl delay_200
-
-init_ddr:
-    ldr r2, =0x0000001A // reset DDR
-    ldr r1, =0x6D000010
-    str r2, [r1]
-
-    ldr r1, =0x6D000014 // SDRC_SYSSTATUS
-wait_reset:
-    ldr r2, [r1]
-    tst r2, #1 // test RESETDONE
-    beq wait_reset
-
-    ldr r2, =0x00000018 // release DDR reset
-    ldr r1, =0x6D000010
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x00000100 // 32-bit SDRAM on data lane [31:0] - CS0
-    ldr r1, =0x6D000044
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x02584099 // SDRC_MCFG0 register
-    ldr r1, =0x6D000080
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x00054601 // SDRC_RFR_CTRL0 register
-    ldr r1, =0x6D0000a4
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0xA29DB4C6 // SDRC_ACTIM_CTRLA0 register
-    ldr r1, =0x6D00009c
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x00012214 // SDRC_ACTIM_CTRLB0 register
-    ldr r1, =0x6D0000A0
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x00000081 // Disble Power Down of CKE due to 1 CKE on combo part
-    ldr r1, =0x6D000070
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x00000000 // NOP command
-    ldr r1, =0x6D0000A8
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x00000001 // Precharge command
-    ldr r1, =0x6D0000A8
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x00000002 // Auto-refresh command
-    ldr r1, =0x6D0000A8
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x00000002 // Auto-refresh command
-    ldr r1, =0x6D0000A8
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x00000032 // SDRC MR0 register Burst length=4
-    ldr r1, =0x6D000084
-    str r2, [r1]
-
- bl delay_200
-
-    ldr r2, =0x0000000A // SDRC DLLA control register
-    ldr r1, =0x6D000060
-    str r2, [r1]
-
- bl delay_200
-
 /********************************************************************/

 midstart:
@@ -369,7 +180,8 @@ warmstart:

     mov r0, r11
 jump_to_c:
-    bl start
+    bl target_putchar_loop
+    //bl start

     /* the C code should never return */
     b reset
-- 
2.3.3


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