[PATCH 15/16] Added defines for EMIF0 subsystem in am335x.h

[Jarielle Catbagan]

Added defines for EMIF0 register base address and register offsets.

---
 ports/beagleboneblack/am335x.h    | 48 +++++++++++++++++++++++++++++++++++++++
 ports/beagleboneblack/config.h    |  2 +-
 ports/beagleboneblack/rom_reset.S |  6 ++---
 3 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/ports/beagleboneblack/am335x.h b/ports/beagleboneblack/am335x.h
index 9dc0649..37aa024 100644
--- a/ports/beagleboneblack/am335x.h
+++ b/ports/beagleboneblack/am335x.h
@@ -37,6 +37,54 @@


 /*=====================================================================================*/
+/* EMIF0 Configuration Registers */
+/*=====================================================================================*/
+#define EMIF0_BASE 0x4C000000
+#define EMIFO_REG(_x_) *(vulong *)(EMIFO_BASE + _x_)
+/*-------------------------------------------------------------------------------------*/
+/* EMIFO Register offsets */
+#define EMIF_MOD_ID_REV 0x0000
+#define STATUS 0x0004
+#define SDRAM_CONFIG 0x0008
+#define SDRAM_CONFIG_2 0x000C
+#define SDRAM_REF_CTRL 0x0010
+#define SDRAM_REF_CTRL_SHOW 0x0014
+#define SDRAM_TIM_1 0x0018
+#define SDRAM_TIM_1_SHDW 0x001C
+#define SDRAM_TIM_2 0x0020
+#define SDRAM_TIM_2_SHDW 0x0024
+#define SDRAM_TIM_3 0x0028
+#define SDRAM_TIM_3_SHDW 0x002C
+#define PWR_MGMT_CTRL 0x0038
+#define PWR_MGMT_CTRL_SHDW 0x003C
+#define INTERFACE_CONFIG 0x0054
+#define INTERFACE_CONFIG_VAL_1 0x0058
+#define INTERFACE_CONFIG_VAL_2 0x005C
+#define PERF_CNT_1 0x0080
+#define PERF_CNT_2 0x0084
+#define PERF_CNT_CFG 0x0088
+#define PERF_CNT_SEL 0x008C
+#define PERF_CNT_TIM 0x0090
+#define READ_IDLE_CTRL 0x0098
+#define READ_IDLE_CTRL_SHDW 0x009C
+#define IRQSTATUS_RAW_SYS 0x00A4
+#define IRQSTATUS_SYS 0x00AC
+#define IRQENABLE_SET_SYS 0x00B4
+#define IRQENABLE_CLR_SYS 0x00BC
+#define ZQ_CONFIG 0x00C8
+#define RW_LVL_RAMP_WNDW 0x00D4
+#define RW_LVL_RAMP_CTRL 0x00D8
+#define RW_LVL_CTRL 0x00DC
+#define DDR_PHY_CTRL_1 0x00E4
+#define DDR_PHY_CTRL_1_SHDW 0x00E8
+#define PRIORITY_TO_CLASS_SRVC_MAP 0x0100
+#define CONN_ID_TO_CLASS_SRVC_1_MAP 0x0104
+#define CONN_ID_TO_CLASS_SRVC_2_MAP 0x0108
+#define RW_EXEC_THRESHOLD 0x0120
+/*=====================================================================================*/
+
+
+/*=====================================================================================*/
 /* McASPx Data Registers */
 /*=====================================================================================*/
 #define MCASP0_DATA_REGS_BASE 0x46000000
diff --git a/ports/beagleboneblack/config.h b/ports/beagleboneblack/config.h
index 754aeb6..6c57d2e 100644
--- a/ports/beagleboneblack/config.h
+++ b/ports/beagleboneblack/config.h
@@ -173,7 +173,7 @@
  // a hardware-resident clock whose rate is defined by
  // TIMER_TICKS_PER_MSEC
 #define INCLUDE_GDB 0 // enable 'gdb' command, incomplete facility
with the eventual
- goal of hooking up to a gdb debugger
+ // goal of hooking up to a gdb debugger
 #define INCLUDE_ICMP 0
 #define INCLUDE_JFFS2 0
 #define INCLUDE_JFFS2ZLIB 0
diff --git a/ports/beagleboneblack/rom_reset.S
b/ports/beagleboneblack/rom_reset.S
index 199cc87..a4ac0db 100644
--- a/ports/beagleboneblack/rom_reset.S
+++ b/ports/beagleboneblack/rom_reset.S
@@ -56,7 +56,6 @@
 /*********************************************************************/

     .extern start
-    .extern target_putchar_loop

     .global reset
     .global coldstart
@@ -96,6 +95,8 @@ coldstart_1:

 // bl cache_init

+// perform DDR3 initialization here
+
 /********************************************************************/

 midstart:
@@ -180,8 +181,7 @@ warmstart:

     mov r0, r11
 jump_to_c:
-    bl target_putchar_loop
-    //bl start
+    bl start

     /* the C code should never return */
     b reset
-- 
2.3.3