[PATCH 13/13] Removed bdi2000.cfg in BBB port as it does not target the AM335x
Jarielle Catbagan
jcatbagan93 at gmail.com
Sat Jun 20 02:58:03 UTC 2015
---
ports/beagleboneblack/bdi2000.cfg | 188 --------------------------------------
1 file changed, 188 deletions(-)
delete mode 100644 ports/beagleboneblack/bdi2000.cfg
diff --git a/ports/beagleboneblack/bdi2000.cfg b/ports/beagleboneblack/bdi2000.cfg
deleted file mode 100644
index 93a82cf..0000000
--- a/ports/beagleboneblack/bdi2000.cfg
+++ /dev/null
@@ -1,188 +0,0 @@
-; bdiGDB configuration for TI OMAP3430 ES1.0
-; ------------------------------------------
-;
-; To halt the core as soon as possible after power-up,
-; select EMU1=1,EMU0=0 (Wait In Reset mode WIR).
-;
-; Commands supported in the SCANINIT and SCANPOST strings:
-;
-; I<n>=<...b2b1b0> write IR, b0 is first scanned
-; D<n>=<...b2b1b0> write DR, b0 is first scanned
-; n : the number of bits 1..256
-; bx : a data byte, two hex digits
-; W<n> wait for n (decimal) micro seconds
-; T1 assert TRST
-; T0 release TRST
-; R1 assert RESET
-; R0 release RESET
-; CH<n> clock TCK n (decimal) times with TMS high
-; CL<n> clock TCK n (decimal) times with TMS low
-;
-;
-[INIT]
-WREG CPSR 0x000001D3 ;select ARM / supervisor mode
-
-WM32 0x48314048 0x0000aaaa ;disable watchdog WDT2
-WM32 0x48314048 0x00005555 ;disable watchdog WDT2
-
-WGPR 11 0x40200020 ;set frame pointer to free RAM
-WM32 0x40200020 0x40200028 ;dummy stack frame
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;; Initialize Pins
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-WM32 0x48002170 0x01190019 ; Enable UART2 RX and TX
-WM32 0x48002a18 0x0018010f ; Enable SYS_CLKOUT1
-WM32 0x480021e0 0x0018010f ; Enable SYS_CLKOUT2
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;; Initialize Clocks
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;WM32 0x48306d70 0x00000000 ; disable sys_clk1
-;WM32 0x4830729C 0x00000006 ; set polarity
-WM32 0x48306814 0x00000000 ; Enable Interface clock to be Free running
-WM32 0x48004e10 0x00000001 ; Enable L3_ICLK and L4_ICLK
-WM32 0x48004a30 0x00006000 ; Enable Auto Clock for UART1 and UART2
-;WM32 0x48004d70 0x00000000 ; Enable source for SYS_CLKOUT2
-;WM32 0x48004d70 0x00000080 ; Enable SYS_CLKOUT2
-WM32 0x48004a00 0xc3fffe01 ; Turn on all available module clocks
-WM32 0x48004a10 0x7ffffedb ; Turn on all available peripheral clocks
-;WM32 0x48306d70 0x00000080 ; enable sys_clk1
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Initialize CS0
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-WM32 0x6E000010 0x08 ; Set No-idle, Normal Mode, CLK free running
-WM32 0x6E000078 0x00000C48 ; Config7
-WM32 0x6E000060 0x00001200 ; Config1
-WM32 0x6E000064 0x000f0f01 ; Config2
-WM32 0x6E000068 0x00020201 ; Config3
-WM32 0x6E00006C 0x0C060C06 ; Config4
-WM32 0x6E000070 0x01131F1F ; Config5
-WM32 0x6E000074 0x0F030000 ; Config6
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Initialize DDR
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;/* SDRAM software reset */
-;/* No idle ack and RESET enable */
-;__raw_writel(0x1A, SDRC_REG(SYSCONFIG));
-WM32 0x6D000010 0x0000001A ; reset DDR
-;sdelay(100);
-DELAY 100
-;/* No idle ack and RESET disable */
-;__raw_writel(0x18, SDRC_REG(SYSCONFIG));
-WM32 0x6D000010 0x00000018 ; release reset
-DELAY 100
-;
-;/* SDRC Sharing register */
-;/* 32-bit SDRAM on data lane [31:0] - CS0 */
-;/* pin tri-stated = 1 */
-;__raw_writel(0x00000100, SDRC_REG(SHARING));
-WM32 0x6D000044 0x00000100
-;
-;/* ----- SDRC Registers Configuration --------- */
-;/* SDRC_MCFG0 register */
-;__raw_writel(0x02584099, SDRC_REG(MCFG_0));
-WM32 0x6D000080 0x02584099
-;
-;/* SDRC_RFR_CTRL0 register */
-;__raw_writel(0x54601, SDRC_REG(RFR_CTRL_0));
-WM32 0x6D0000a4 0x00054601
-;
-;/* SDRC_ACTIM_CTRLA0 register */
-;__raw_writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
-WM32 0x6D00009c 0xA29DB4C6
-;
-;/* SDRC_ACTIM_CTRLB0 register */
-;__raw_writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
-WM32 0x6D0000A0 0x00012214
-;
-;/* Disble Power Down of CKE due to 1 CKE on combo part */
-;__raw_writel(0x00000081, SDRC_REG(POWER));
-WM32 0x6D000070 0x00000081
-;
-;/* SDRC_MANUAL command register */
-;/* NOP command */
-;__raw_writel(0x00000000, SDRC_REG(MANUAL_0));
-WM32 0x6D0000A8 0x00000000
-;
-;/* Precharge command */
-;__raw_writel(0x00000001, SDRC_REG(MANUAL_0));
-WM32 0x6D0000A8 0x00000001
-;
-;/* Auto-refresh command */
-;__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
-WM32 0x6D0000A8 0x00000002
-;
-;/* Auto-refresh command */
-;__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
-WM32 0x6D0000A8 0x00000002
-;
-;/* SDRC MR0 register Burst length=4 */
-;__raw_writel(0x00000032, SDRC_REG(MR_0));
-WM32 0x6D000084 0x00000032
-;
-;/* SDRC DLLA control register */
-;__raw_writel(0x0000000A, SDRC_REG(DLLA_CTRL));
-WM32 0x6D000060 0x0000000A
-
-[TARGET]
-CPUTYPE OMAP3430
-CLOCK 1 ; JTAG clock
-POWERUP 2000 ; power-up delay
-TRST PUSHPULL ; TRST driver type (OPENDRAIN | PUSHPULL)
-RESET HARD ; NONE | HARD <n> (ms)
-STARTUP HALT ; let boot code setup the system
-;STARTUP RUN ; let boot code setup the system
-ENDIAN LITTLE ; memory model (LITTLE | BIG)
-;MEMACCESS CORE 10 ; memory access via core (8 TCK's access delay)
-MEMACCESS AHB 8 ; memory access via AHB (64 TCK's access delay)
-;VECTOR CATCH 0x1B ; catch Abort, Undef, Reset
-
-SCANPRED 1 6 ; count for ICEPick TAP
-SCANSUCC 1 8 ; Xilinx
-
-; Configure ICEPick module to make Cortex-A8 DAP-TAP visible
-SCANINIT t1:w1000:t0:w1000: ; toggle TRST,
-SCANINIT ch10:w1000: ; clock TCK with TMS high and wait
-SCANINIT i6=07:d8=89:i6=02: ; connect and select router
-SCANINIT d32=81000080: ; IP control: KeepPowered
-SCANINIT d32=a3002048: ; TAP3: DebugConnect, ForcePower, ForceActive
-SCANINIT d32=81000081: ; IP control: KeepPowered, SysReset
-SCANINIT d32=a3002148: ; enable TAP3
-SCANINIT cl10:i10=ffff ; clock 10 times in RTI, scan bypass
-
-;assert SysSeset after debugger has setup
-;SCANPOST i10=ffff: ; scan bypass
-;SCANPOST i10=002f: ; IP(router) - TAP3(bypass)
-;SCANPOST d33=0102000102: ; IP control = SysReset
-;SCANPOST i10=ffff ; scan bypass
-
-[HOST]
-IP 192.168.1.3
-FILE build_csb740\ramtst.elf
-FORMAT ELF
-LOAD MANUAL ;load file MANUAL or AUTO after reset
-PROMPT CSB740_>
-TELNET NOECHO
-
-[FLASH]
-WORKSPACE 0x80001000 ;workspace at 0x1000
-CHIPSIZE 0x4000000
-CHIPTYPE MIRRORX16
-BUSWIDTH 16
-FILE build_csb740\boot.bin
-FORMAT BIN 0x08000000
-ERASE 0x08000000
-ERASE 0x08020000
-ERASE 0x08040000
-ERASE 0x08060000
-ERASE 0x08080000
-
-[REGS]
-FILE C:\els\abatron\arm11\regOMAP3430.def
--
2.3.3
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