[PATCH 04/13] Removed all omap3530_* peripheral source and header files from BBB port

Jarielle Catbagan jcatbagan93 at gmail.com
Sat Jun 20 02:57:54 UTC 2015


Additionally, the compilation of these files were excluded in the Makefile
---
 ports/beagleboneblack/Makefile         |    3 +-
 ports/beagleboneblack/omap3530_gpio.c  |  329 ----------
 ports/beagleboneblack/omap3530_iomux.c |  530 ----------------
 ports/beagleboneblack/omap3530_iomux.h | 1077 --------------------------------
 ports/beagleboneblack/omap3530_lcd.c   |  342 ----------
 ports/beagleboneblack/omap3530_lcd.h   |   75 ---
 ports/beagleboneblack/omap3530_mem.h   |  184 ------
 ports/beagleboneblack/omap3530_sdmmc.c |  505 ---------------
 8 files changed, 1 insertion(+), 3044 deletions(-)
 delete mode 100644 ports/beagleboneblack/omap3530_gpio.c
 delete mode 100644 ports/beagleboneblack/omap3530_iomux.c
 delete mode 100644 ports/beagleboneblack/omap3530_iomux.h
 delete mode 100644 ports/beagleboneblack/omap3530_lcd.c
 delete mode 100644 ports/beagleboneblack/omap3530_lcd.h
 delete mode 100644 ports/beagleboneblack/omap3530_mem.h
 delete mode 100644 ports/beagleboneblack/omap3530_sdmmc.c

diff --git a/ports/beagleboneblack/Makefile b/ports/beagleboneblack/Makefile
index b384156..2fceca3 100644
--- a/ports/beagleboneblack/Makefile
+++ b/ports/beagleboneblack/Makefile
@@ -42,8 +42,7 @@ include	$(TOPDIR)/make/common.make
 #
 LOCSSRC		= 
 CPUSSRC		= vectors_arm.S
-LOCCSRC		= ad7843.c cpuio.c etherdev.c nand740.c omap3530_gpio.c \
-			  omap3530_lcd.c omap3530_sdmmc.c
+LOCCSRC		= ad7843.c cpuio.c etherdev.c nand740.c 
 COMCSRC		= arp.c cast.c cache.c chario.c cmdtbl.c \
 			  docmd.c dhcp_00.c dhcpboot.c dns.c edit.c env.c ethernet.c \
 			  flash.c gdb.c icmp.c if.c ledit_vt100.c monprof.c \
diff --git a/ports/beagleboneblack/omap3530_gpio.c b/ports/beagleboneblack/omap3530_gpio.c
deleted file mode 100644
index e1e4315..0000000
--- a/ports/beagleboneblack/omap3530_gpio.c
+++ /dev/null
@@ -1,329 +0,0 @@
-//==========================================================================
-//
-// mx31_gpio.c
-//
-//
-// Author(s):    Luis Torrico, Cogent Computer Systems, Inc.
-// Contributors: 
-// Date:         05/09/2008
-// Description:  This file contains code to intialize the MCIMX31 GPIO
-//               section as well as functions for manipulating the GPIO 
-//               bits
-//
-//--------------------------------------------------------------------------
-
-#include "config.h"
-#include "cpuio.h"
-#include "stddefs.h"
-#include "genlib.h"
-#include "omap3530.h"
-#include "cpu_gpio.h"    // pull in target board specific header
-
-//#define GPIO_DBG
-
-//--------------------------------------------------------
-// GPIO_init()
-//
-// This function sets the startup state for the MCIMX31 GPIO 
-// registers as used on the target CPU.  Refer to cpu_gpio.h 
-// for a description of the default values.  Here we just put
-// them into the chip in the following order:
-// 1. Port x DR	   - Data Register
-// 2. Port x DIR   - Direction Register
-// 3. Port x PSTAT - Pad Status Register
-// 4. Port x ICR1  - GPIO Interrupt Configuration Register 1
-// 5. Port x ICR2  - GPIO Interrupt Configuration Register 2
-// 6. Port x IMASK - GPIO Interrupt Mask Register
-// 7. Port x ISTAT - GPIO Interrupt Status Register
-
-void GPIO_init()
-{
-	// Port 1
-	GPIO1_REG(GPIO_OE)				= PORT1_OE;
-	GPIO1_REG(GPIO_DATAOUT)			= PORT1_DR;
-	//GPIO1_REG(GPIO_CLEARDATAOUT)	= 0;
-	//GPIO1_REG(GPIO_SETDATAOUT)		= 0;
-
-	// Port 2
-	//GPIO2_REG(GPIO_OE)			= 0xFEFFFFFF;
-	GPIO2_REG(GPIO_OE)				= PORT2_OE;
-	GPIO2_REG(GPIO_DATAOUT)			= PORT2_DR;
-	//GPIO2_REG(GPIO_CLEARDATAOUT)	= 0;
-	//GPIO2_REG(GPIO_SETDATAOUT)		= 0;
-
-	// Port 3
-	GPIO3_REG(GPIO_OE)				= PORT3_OE;
-	GPIO3_REG(GPIO_DATAOUT)			= PORT3_DR;
-	//GPIO3_REG(GPIO_CLEARDATAOUT)	= 0;
-	//GPIO3_REG(GPIO_SETDATAOUT)		= 0;
-
-	// Port 4
-	GPIO4_REG(GPIO_OE)				= PORT4_OE;
-	GPIO4_REG(GPIO_DATAOUT)			= PORT4_DR;
-	//GPIO4_REG(GPIO_CLEARDATAOUT)	= 0;
-	//GPIO4_REG(GPIO_SETDATAOUT)		= 0;
-
-	// Port 5
-	GPIO5_REG(GPIO_OE)				= PORT5_OE;
-	GPIO5_REG(GPIO_DATAOUT)			= PORT5_DR;
-	//GPIO5_REG(GPIO_CLEARDATAOUT)	= 0;
-	//GPIO5_REG(GPIO_SETDATAOUT)		= 0;
-
-	// Port 6
-	GPIO6_REG(GPIO_OE)				= PORT6_OE;
-	GPIO6_REG(GPIO_DATAOUT)			= PORT6_DR;
-	//GPIO6_REG(GPIO_CLEARDATAOUT)	= 0;
-	//GPIO6_REG(GPIO_SETDATAOUT)		= 0;
-}
-
-//--------------------------------------------------------
-// GPIO_set()
-//
-// This function sets the desired bit passed in.
-// NOTE: We do not test to see if setting the bit
-// would screw up any alternate functions.  Use 
-// this function with caution!
-//
-
-int GPIO_set(int gpio_bit)
-{
-	// quick sanity test
-#ifdef GPIO_DBG
-	printf("GPIO_set %d.\n", gpio_bit);
-#endif
-	if (gpio_bit > 191) return -1;
-
-	if (gpio_bit < 32)
-	{
-		// Port 1
-		GPIO1_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 0));
-	}
-	else if (gpio_bit < 64)
-	{
-		// Port 2
-		GPIO2_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 32));
-	}
-	else if (gpio_bit < 96)
-	{
-		// Port 3
-		GPIO3_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 64));
-	}
-	else if (gpio_bit < 128)
-	{
-		// Port 4
-		GPIO4_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 96));
-	}
-	else if (gpio_bit < 160)
-	{
-		// Port 5
-		GPIO5_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 128));
-	}
-	else
-	{
-		// Port 6
-		GPIO6_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 160));
-	}
-	return 0;
-}
-
-//--------------------------------------------------------
-// GPIO_clr()
-//
-// This function clears the desired bit passed in.
-//
-
-int GPIO_clr(int gpio_bit)
-{
-#ifdef GPIO_DBG
-	printf("GPIO_clr %d.\n", gpio_bit);
-#endif
- 	// quick sanity test
-	if (gpio_bit > 191) return -1;
-
-	if (gpio_bit < 32)
-	{
-		// Port 1
-		GPIO1_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 0));
-	}
-	else if (gpio_bit < 64)
-	{
-		// Port 2
-		GPIO2_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 32));
-	}
-	else if (gpio_bit < 96)
-	{
-		// Port 3
-		GPIO3_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 64));
-	}
-	else if (gpio_bit < 128)
-	{
-		// Port 4
-		GPIO4_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 96));
-	}
-	else if (gpio_bit < 160)
-	{
-		// Port 5
-		GPIO5_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 128));
-	}
-	else
-	{
-		// Port 6
-		GPIO6_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 160));
-	}
-    return 0;
-}
-//--------------------------------------------------------
-// GPIO_tst()
-//
-// This function returns the state of desired bit passed in.
-// It does not test to see if it's an input or output and thus
-// can be used to verify if an output set/clr has taken place
-// as well as for testing an input state.
-//
-
-int GPIO_tst(int gpio_bit)
-{
-#ifdef GPIO_DBG
-	printf("GPIO_tst %d.\n", gpio_bit);
-#endif
- 	// quick sanity test
-	if (gpio_bit > 191) return -1;
-
-	if (gpio_bit < 32)
-	{
-		// Port 1
-		if (GPIO1_REG(GPIO_DATAIN) & (1 << (gpio_bit - 0))) return 1;
-	}
-	else if (gpio_bit < 64)
-	{
-		// Port 2
-		if (GPIO2_REG(GPIO_DATAIN) & (1 << (gpio_bit - 32))) return 1;
-	}
-	else if (gpio_bit < 96)
-	{
-		// Port 3
-		if (GPIO3_REG(GPIO_DATAIN) & (1 << (gpio_bit - 64))) return 1;
-	}
-	else if (gpio_bit < 128)
-	{
-		// Port 4
-		if (GPIO4_REG(GPIO_DATAIN) & (1 << (gpio_bit - 96))) return 1;
-	}
-	else if (gpio_bit < 160)
-	{
-		// Port 5
-		if (GPIO5_REG(GPIO_DATAIN) & (1 << (gpio_bit - 128))) return 1;
-	}
-	else
-	{
-		// Port 6
-		if (GPIO6_REG(GPIO_DATAIN) & (1 << (gpio_bit - 160))) return 1;
-	}
-	return 0; // bit was not set
-}
-
-//--------------------------------------------------------
-// GPIO_out()
-//
-// This function changes the direction of the desired bit 
-// to output.  NOTE: We do not test to see if changing the
-// direction of the bit would screw up anything.  Use this
-// function with caution!
-//
-// This only worlks if the GPIO has been defined as a GPIO
-// during init.  It will not override the init setting, only
-// change the direction bit
-
-int GPIO_out(int gpio_bit)
-{
-#ifdef GPIO_DBG
-	printf("GPIO_out %d.\n", gpio_bit);
-#endif
-	// quick sanity test
-	if (gpio_bit > 191) return -1;
-
-	if (gpio_bit < 32)
-	{
-		// Port 1
-		GPIO1_REG(GPIO_OE) &= ~(1 << (gpio_bit - 0));
-	}
-	else if (gpio_bit < 64)
-	{
-		// Port 2
-		GPIO2_REG(GPIO_OE) &= ~(1 << (gpio_bit - 32));
-	}
-	else if (gpio_bit < 96)
-	{
-		// Port 3
-		GPIO3_REG(GPIO_OE) &= ~(1 << (gpio_bit - 64));
-	}
-	else if (gpio_bit < 128)
-	{
-		// Port 4
-		GPIO4_REG(GPIO_OE) &= ~(1 << (gpio_bit - 96));
-	}
-	else if (gpio_bit < 160)
-	{
-		// Port 5
-		GPIO5_REG(GPIO_OE) &= ~(1 << (gpio_bit - 128));
-	}
-	else
-	{
-		// Port 6
-		GPIO6_REG(GPIO_OE) &= ~(1 << (gpio_bit - 160));
-	}
-    return 0;
-}
-
-//--------------------------------------------------------
-// GPIO_in()
-//
-// This function changes the direction of the desired bit 
-// to input.  NOTE: We do not test to see if changing the
-// direction of the bit would screw up anything.  Use this
-// function with caution!
-//
-// This only worlks if the GPIO has been defined as a GPIO
-// during init.  It will not override the init setting, only
-// change the direction bit
-int GPIO_in(int gpio_bit)
-{
-#ifdef GPIO_DBG
-	printf("GPIO_in %d.\n", gpio_bit);
-#endif
-	// quick sanity test
-	if (gpio_bit > 191) return -1;
-
-	if (gpio_bit < 32)
-	{
-		// Port 1
-		GPIO1_REG(GPIO_OE) |= (1 << (gpio_bit - 0));
-	}
-	else if (gpio_bit < 64)
-	{
-		// Port 2
-		GPIO2_REG(GPIO_OE) |= (1 << (gpio_bit - 32));
-	}
-	else if (gpio_bit < 96)
-	{
-		// Port 3
-		GPIO3_REG(GPIO_OE) |= (1 << (gpio_bit - 64));
-	}
-	else if (gpio_bit < 128)
-	{
-		// Port 4
-		GPIO4_REG(GPIO_OE) |= (1 << (gpio_bit - 96));
-	}
-	else if (gpio_bit < 160)
-	{
-		// Port 5
-		GPIO5_REG(GPIO_OE) |= (1 << (gpio_bit - 128));
-	}
-	else
-	{
-		// Port 6
-		GPIO6_REG(GPIO_OE) |= (1 << (gpio_bit - 160));
-	}
-	return 0;
-}
-
diff --git a/ports/beagleboneblack/omap3530_iomux.c b/ports/beagleboneblack/omap3530_iomux.c
deleted file mode 100644
index 586ac48..0000000
--- a/ports/beagleboneblack/omap3530_iomux.c
+++ /dev/null
@@ -1,530 +0,0 @@
-//mx31_iomux.c
-
-#include "config.h"
-#include "cpuio.h"
-#include "stddefs.h"
-#include "genlib.h"
-#include "omap3530.h"
-#include "omap3530_iomux.h"
-#include "cpu_gpio.h"    // pull in target board specific header
-
-void iomux_init()
-{
-
-// Initialization of GPR for CSB733
-IOMUX_CTL_REG(GENERAL_REGISTER) = WEIM_ON_CS3_EN | CSPI1_ON_UART_EN;
-
-// MX31_PIN_TTM_PAD = can not be written to.
-// cspi_miso = U2_RXD, cspi3_sclk = U2_RTS, cspi3_spi_rdy = U2_CTS, ttm_pad = default
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER1) = MX31_PIN_CSPI3_MISO((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
-									| MX31_PIN_CSPI3_SCLK((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
-									| MX31_PIN_CSPI3_SPI_RDY((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE));
-//									| MX31_PIN_TTM_PAD();
-
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER1) = MX31_PIN_CSPI3_MISO(0x20)
-//									| MX31_PIN_CSPI3_SCLK(0x20)
-//									| MX31_PIN_CSPI3_SPI_RDY(0x20);
-////									| MX31_PIN_TTM_PAD();
-
-// MX31_PIN_CLKSS and MX31_PIN_CE_CONTROL = can not be written to.
-// reset_b = NC, ce_control = default, ctl_clkss = default, cspi3_mosi = U2_RXD
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER2) = MX31_PIN_ATA_RESET_B((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_CE_CONTROL((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-//									| MX31_PIN_CLKSS()
-									| MX31_PIN_CSPI3_MOSI((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1));
-
-// ata_cs1 = NC, ata_dior = D_TXD, ata_diow = NC, ata, dmack = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER3) = MX31_PIN_ATA_CS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_ATA_DIOR((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
-									| MX31_PIN_ATA_DIOW((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_ATA_DMACK((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// sd1_data1 = SD_D1, sd1_data2 = SD_D2, sd1_data3 = SD_D3, ata_cs0 = D_RXD
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER4) = MX31_PIN_SD1_DATA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SD1_DATA2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SD1_DATA3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_ATA_CS0((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1));
-
-// d3_spl = NC, sd1_cmd = SD_CMD, sd1_clk - SD_CLK, sd1_data0 = SD_D0
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER5) = MX31_PIN_D3_SPL((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_SD1_CMD((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SD1_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
-									| MX31_PIN_SD1_DATA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// vsync3 = LCD_VSYNC, contrast = NC, d3_rev = NC, d3_cls = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER6) = MX31_PIN_VSYNC3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CONTRAST((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_D3_REV((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_D3_CLS((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
-
-// ser_rs = NC, par_rs = NC, write = NC, read = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER7) = MX31_PIN_SER_RS((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_PAR_RS((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_WRITE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_READ((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// sd_d_io = NC, sd_d_clk = NC, lcs0 = NC, lcs1 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER8) = MX31_PIN_SD_D_IO((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_SD_D_CLK((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_LCS0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_LCS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// hsync = LCD_HSYNC, fpshift = LCD_PCLK, drdy0 = LCD_OE, sd_d_i = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER9) = MX31_PIN_HSYNC((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
-									| MX31_PIN_FPSHIFT((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
-									| MX31_PIN_DRDY0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SD_D_I((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// ld15 = LCD_R3, ld16 = LCD_R4, ld17 = LCD_R5, sd_d_i = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER10) = MX31_PIN_LD15((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD16((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD17((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_VSYNC0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// ld11 = LCD_G5, ld12 = LCD_R0, ld13 = LCD_R1, ld14 = LCD_R2
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER11) = MX31_PIN_LD11((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD12((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD13((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD14((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// ld7 = LCD_G1, ld8 = LCD_G2, ld9 = LCD_G3, ld10 = LCD_G4
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER12) = MX31_PIN_LD7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD8((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD9((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// ld3 = LCD_B3, ld4 = LCD_B4, ld5 = LCD_B5, ld6 = LCD_G0
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER13) = MX31_PIN_LD3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// usbh2_data1 = UH2_D1, ld0 = LCD_B0, ld1 = LCD_B1, ld2 = LCD_B0
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER14) = MX31_PIN_USBH2_DATA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_LD2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// usbh2_dir = UH2_DIR, usbh2_stp = UH2_STP, usbh2_nxt = UH2_NXT, usbh2_data0 = UH2_D0
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER15) = MX31_PIN_USBH2_DIR((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
-									| MX31_PIN_USBH2_STP((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBH2_NXT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBH2_DATA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// usbotg_data5 = UD_D5, usbotg_data6 = UD_D6, usbotg_data7 = UD_D7, usbh2_clk = UH2_CLK
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER16) = MX31_PIN_USBOTG_DATA5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBOTG_DATA6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBOTG_DATA7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBH2_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// usbotg_data1 = UD_D1, usbotg_data2 = UD_D2, usbotg_data3 = UD_D3, usbotg_data4 = UD_D4
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER17) = MX31_PIN_USBOTG_DATA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBOTG_DATA2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBOTG_DATA3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBOTG_DATA4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// usbotg_dir = UD_DIR, usbotg_stp = UD_STP, usbotg_nxt = UD_NXT, usbotg_data0 = UD_D0
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER18) = MX31_PIN_USBOTG_DIR((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBOTG_STP((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
-									| MX31_PIN_USBOTG_NXT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_USBOTG_DATA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// usb_pwr = NC, usb_oc = CF_RST, usb_byp = NC, usbotg_clk = UD_CLK
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER19) = MX31_PIN_USB_PWR((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_USB_OC((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_USB_BYP((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_USBOTG_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// MX31_PIN_TDO and MX31_PIN_SJC_MOD = can not be written to
-// tdo = TDO_C, trstb = TRST_C, de_b = TP1, sjc_mod = GND
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER20) = MX31_PIN_TDO()
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER20) = MX31_PIN_TRSTB((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_DE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-//									| MX31_PIN_SJC_MOD();
-
-// MX31_PIN_RTCK = can not be written to.
-// rtck = NC, tck = TCK_C, tms = TMS_C, tdi = TDI_C
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER21) = MX31_PIN_RTCK()
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER21) = MX31_PIN_TCK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_TMS((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_TDI((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// key_col4 = NC, key_col5 = NC, key_col6 = NC, key_col7 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER22) = MX31_PIN_KEY_COL4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_KEY_COL5((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_KEY_COL6((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_KEY_COL7((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// key_col0 = NC, key_col1 = NC, key_col2 = NC, key_col3 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER23) = MX31_PIN_KEY_COL0((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_KEY_COL1((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_KEY_COL2((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_KEY_COL3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
-
-// key_row4 = NC, key_row5 = NC, key_row6 = NC, key_row7 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER24) = MX31_PIN_KEY_ROW4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_KEY_ROW5((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_KEY_ROW6((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_KEY_ROW7((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// key_row0 = NC, key_row1 = NC, key_row2 = NC, key_row3 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER25) = MX31_PIN_KEY_ROW0((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_KEY_ROW1((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_KEY_ROW2((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_KEY_ROW3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
-
-// txd2 = U1_TXD, rts2 = U1_RTS, cts2 = U1_CTS, batt_line = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER26) = MX31_PIN_TXD2((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
-									| MX31_PIN_RTS2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CTS2((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
-									| MX31_PIN_BATT_LINE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// ri_dte1, dcd_dte1, and dtr_dce2 are set to CSPI1 signals by GPR(2)
-// rxd2 = U1_RXD
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER27) = MX31_PIN_RI_DTE1()
-//									| MX31_PIN_DCD_DTE1()
-//									| MX31_PIN_DTR_DCE2()
-//									| MX31_PIN_RXD2(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC);
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER27) = MX31_PIN_RXD2((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC));
-
-// dtr_dte1 and dsr_dte1 are set to CSPI1 signals by GPR(2)
-// ri_dce1 = SPI0_RDY, dcd_dce1 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER28) = MX31_PIN_RI_DCE1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
-									| MX31_PIN_DCD_DCE1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-//									| MX31_PIN_DTR_DTE1()
-//									| MX31_PIN_DSR_DTE1();
-
-// rts1 = U0_RTS, cts1 = U0_CTS, dtr_dce1 = NC, dsr_dce1 = SPI0_CLK
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER29) = MX31_PIN_RTS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CTS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
-									| MX31_PIN_DTR_DCE1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_DSR_DCE1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1));
-
-// cspi2_sclk = SPI1_CLK, cspi2_spi_rdy = SPI1_RDY, rxd1 = U0_RXD, txd1 = U0_TXD
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER30) = MX31_PIN_CSPI2_SCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSPI2_SPI_RDY((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_RXD1((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC))
-									| MX31_PIN_TXD1((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE));
-
-// cspi2_miso = SPI1_MISO, cspi2_ss0 = SPI1_CS0, cspi2_ss1 = SPI1_CS1, cspi2_ss2 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER31) = MX31_PIN_CSPI2_MISO((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSPI2_SS0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSPI2_SS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSPI2_SS2((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
-
-// cspi1_ss2 = UH1_RCV, cspi1_sclk = UH1_OE, cspi1_spi_rdy = UH1_FS, cspi2_mosi = SPI1_MOSI
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER32) = MX31_PIN_CSPI1_SS2((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
-									| MX31_PIN_CSPI1_SCLK((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
-									| MX31_PIN_CSPI1_SPI_RDY((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
-									| MX31_PIN_CSPI2_MOSI((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// cspi1_mosi = UH1_RXDM, cspi1_miso = UH1_RXDP, cspi1_ss0 = UH1_TXDM, cspi1_ss1 = UH1_TXDP
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER33) = MX31_PIN_CSPI1_MOSI((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1))
-									| MX31_PIN_CSPI1_MISO((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1))
-									| MX31_PIN_CSPI1_SS0((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
-									| MX31_PIN_CSPI1_SS1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE));
-
-// stxd6 = AC_SDOUT, srxd6 = AC_SDIN, sck6 = AC_BCLK, sfs6 = AC_SYNC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER34) = MX31_PIN_STXD6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SRXD6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SCK6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SFS6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// stxd5 = SSI_TXD, srxd5 = SSI_RXD, sck5 = SSI_CLK, sfs5 = SSI_FRM
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER35) = MX31_PIN_STXD5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SRXD5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SCK5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SFS5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// stxd4 = NC, srxd4 = NC, sck4 = SSI_MCLK, sfs4 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER36) = MX31_PIN_STXD4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_SRXD4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_SCK4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SFS4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// stxd3 = AC_RST, srxd3 = NC, sck3 = NC, sfs3 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER37) = MX31_PIN_STXD3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_SRXD3((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_SCK3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_SFS3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
-
-// csi_hsync = VIP_HSYNC, csi_pixclk = VIP_PCLK, i2c_clk = I2C_SCL, i2c_dat = I2C_SDA
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER38) = MX31_PIN_CSI_HSYNC((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_PIXCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_I2C_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_I2C_DAT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// csi_d14 = VIP_D8, csi_d15 = VIP_D9, csi_mclk = VIP_MCLK, csi_vsync = VIP_VSYNC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER39) = MX31_PIN_CSI_D14((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_D15((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_MCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
-									| MX31_PIN_CSI_VSYNC((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// csi_d10 = VIP_D4, csi_d11 = VIP_D5, csi_D12 = VIP_D6, csi_D13 = VIP_D7
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER40) = MX31_PIN_CSI_D10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_D11((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_D12((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_D13((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// csi_d6 = VIP_D0, csi_d7 = VIP_D1, csi_D8 = VIP_D2, csi_D9 = VIP_D3
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER41) = MX31_PIN_CSI_D6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_D7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_D8((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_D9((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// m_request = NC, m_grant = NC, csi_d4 = NC, csi_d5 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER42) = MX31_PIN_M_REQUEST((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_M_GRANT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CSI_D4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_CSI_D5((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// pc_rst = UH2_D5, isis16 = UH2_D6, pc_rw_b = UH2_D7, pc_poe = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER43) = MX31_PIN_PC_RST((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
-									| MX31_PIN_IOIS16((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
-									| MX31_PIN_PC_RW_B((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
-									| MX31_PIN_PC_POE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// pc_vs1 = NC, pc_vs2 = UH2_D2, pc_bvd1 = UH2_D3, pc_bvd2 = UH2_D4
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER44) = MX31_PIN_PC_VS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_PC_VS2((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
-									| MX31_PIN_PC_BVD1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
-									| MX31_PIN_PC_BVD2((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1));
-
-// pc_cd2_b = CF_CD, pc_wait_b = CF_WAIT, pc_ready = CF_RDY, pc_pwron = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER45) = MX31_PIN_PC_CD2_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_PC_WAIT_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_PC_READY((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_PC_PWRON((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// d2, d1, and d0 are not writable, reset values are correct.
-// d2 = LD2, d1 = LD1, d0 = LD0, pc_cd1_b = CF_CD
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER46) = MX31_PIN_D2()
-//									| MX31_PIN_D1()
-//									| MX31_PIN_D0()
-//									| MX31_PIN_PC_CD1_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-
-// d6, d5, d4 and d3 are not writable, reset values are correct.
-// d6 = LD6, d5 = LD5, d4 = LD4, d3 = LD3
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER47) = MX31_PIN_D6()
-//									| MX31_PIN_D5()
-//									| MX31_PIN_D4()
-//									| MX31_PIN_D3();
-
-// d10, d9, d8 and d7 are not writable, reset values are correct.
-// d10 = LD10, d9 = LD9, d8 = LD8, d7 = LD7
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER48) = MX31_PIN_D10()
-//									| MX31_PIN_D9()
-//									| MX31_PIN_D8()
-//									| MX31_PIN_D7();
-
-// d14, d13, d12 and d11 are not writable, reset values are correct.
-// d14 = LD14, d13 = LD13, d12 = LD12, d11 = L11
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER49) = MX31_PIN_D14()
-//									| MX31_PIN_D13()
-//									| MX31_PIN_D12()
-//									| MX31_PIN_D11();
-
-// d15 is not writable, reset value is correct.
-// nfwp_b = *N_WP, nfce_b = *N_CE, nfrb = N_RDY, d15 = LD15
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER50) = MX31_PIN_NFWP_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_NFCE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_NFRB((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-//									| MX31_PIN_D15();
-
-// nfwe_b = *N_WE, nfre_b = *N_RE, nfale = N_ALE, nfcle = N_CLE
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER51) = MX31_PIN_NFWE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_NFRE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_NFALE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_NFCLE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// sdqs0, sdqs1, sdqs2, and sdqs3 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER52) = MX31_PIN_SDQS0()
-//									| MX31_PIN_SDQS1()
-//									| MX31_PIN_SDQS2()
-//									| MX31_PIN_SDQS3();
-
-// sdclk_b is not writable, reset value is correct.
-// sdcke0 = SDCKE, sdcke1 = NC, sdclk = SDCLK, sdclk_b = *SDCLK
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER53) = MX31_PIN_SDCKE0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SDCKE1((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC))
-									| MX31_PIN_SDCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-//									| MX31_PIN_SDCLK_B();
-
-// rw = *WE, ras = *SDRAS, cas = *SDCAS, sdwe = *SDWE
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER54) = MX31_PIN_RW((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_RAS((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CAS((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SDWE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// ecb is not writable, reset value is correct.
-// cs5 = *CS5, ecb = ECB, lba = LBA, bclk = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER55) = MX31_PIN_CS5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-//									| MX31_PIN_ECB()
-									| MX31_PIN_LBA((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_BCLK((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// cs1 = *CS1, cs2 = *SDCS, cs3 = NC, cs4 = *DTACK
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER56) = MX31_PIN_CS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CS2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CS3((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_CS4((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1));
-
-// eb0 = *BE0, eb1 = *BE1, oe = *OE, cs0 = *CS0
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER57) = MX31_PIN_EB0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_EB1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_OE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_CS0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// dqm0 = DQM0, dqm1 = DQM1, dqm2 = DQM2, dqm3 = DQM3
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER58) = MX31_PIN_DQM0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_DQM1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_DQM2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_DQM3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// sd28, sd29, sd30 and sd31 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER59) = MX31_PIN_SD28()
-//									| MX31_PIN_SD29()
-//									| MX31_PIN_SD30()
-//									| MX31_PIN_SD31();
-
-// sd24, sd25, sd26 and sd27 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER60) = MX31_PIN_SD24()
-//									| MX31_PIN_SD25()
-//									| MX31_PIN_SD26()
-//									| MX31_PIN_SD27();
-
-// sd20, sd21, sd22 and sd23 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER61) = MX31_PIN_SD20()
-//									| MX31_PIN_SD21()
-//									| MX31_PIN_SD22()
-//									| MX31_PIN_SD23();
-
-// sd16, sd17, sd18 and sd19 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER62) = MX31_PIN_SD16()
-//									| MX31_PIN_SD17()
-//									| MX31_PIN_SD18()
-//									| MX31_PIN_SD19();
-
-// sd12, sd13, sd14 and sd15 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER63) = MX31_PIN_SD12()
-//									| MX31_PIN_SD13()
-//									| MX31_PIN_SD14()
-//									| MX31_PIN_SD15();
-
-// sd8, sd9, sd10 and sd11 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER64) = MX31_PIN_SD8()
-//									| MX31_PIN_SD9()
-//									| MX31_PIN_SD10()
-//									| MX31_PIN_SD11();
-
-// sd4, sd5, sd6 and sd7 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER65) = MX31_PIN_SD4()
-//									| MX31_PIN_SD5()
-//									| MX31_PIN_SD6()
-//									| MX31_PIN_SD7();
-
-// sd0, sd1, sd2 and sd3 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER66) = MX31_PIN_SD0()
-//									| MX31_PIN_SD1()
-//									| MX31_PIN_SD2()
-//									| MX31_PIN_SD3();
-
-// a24 = A24, a25 = A25, sdba1 = SDBA1, sdba0 = SDBA0
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER67) = MX31_PIN_A24((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A25((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SDBA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_SDBA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// address lines are one to one.
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER68) = MX31_PIN_A20((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A21((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A22((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A23((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// address lines are one to one.
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER69) = MX31_PIN_A16((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A17((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A18((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A19((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// address lines are one to one.
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER70) = MX31_PIN_A12((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A13((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A14((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A15((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// address lines are one to one.
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER71) = MX31_PIN_A9((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_MA10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A11((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// address lines are one to one.
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER72) = MX31_PIN_A5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A8((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// address lines are one to one.
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER73) = MX31_PIN_A1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
-									| MX31_PIN_A4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// dvfs1 = NC, vpg0 = NC, vpg1 = NC, a0 = A0
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER74) = MX31_PIN_DVFS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_VPG0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_VPG1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_A0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-
-// ckil and power_fail are not writable, reset values are correct.
-//ckil = 32K, power_fail = PWR_FAIL, vstby = VSTBY, dvfs0 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER75) = MX31_PIN_CKIL()
-//									| MX31_PIN_POWER_FAIL()
-//									| MX31_PIN_VSTBY(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_DVFS0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-
-// boot_mode1, boot_mode2, boot_mode3, and boot_mode4 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER76) = MX31_PIN_BOOT_MODE1()
-//									| MX31_PIN_BOOT_MODE2()
-//									| MX31_PIN_BOOT_MODE3()
-//									| MX31_PIN_BOOT_MODE4();
-
-// por_b, clko, and boot_mode0 are not writable, reset values are correct.
-// reset_in_b = *RST_IN (this is set in the GPR)
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER77) = MX31_PIN_RESET_IN_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
-//									| MX31_PIN_POR_B()
-//									| MX31_PIN_CLKO()
-//									| MX31_PIN_BOOT_MODE0();
-
-// ckih is not writable, reset value is correct.
-// stx0 = GPIO1, srx0 = GPIO4, simpd0 = GPIO5
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER78) = MX31_PIN_STX0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_SRX0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_SIMPD0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-//									| MX31_PIN_CKIH();
-
-// gpio3_1 = VF_EN, sclk0 = GPIO8, srst0 = GPIO9, sven0 = GPIO0 (USR_LED)
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER79) = MX31_PIN_GPIO3_1((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
-									| MX31_PIN_SCLK0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_SRST0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_SVEN0((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
-
-// gpio1_4 = UH1_SUSP, gpio1_5 = PWR_RDY, gpio1_6 = UH1_MODE, gpio3_0 = NC
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER80) = MX31_PIN_GPIO1_4((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
-									| MX31_PIN_GPIO1_5((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC))
-									| MX31_PIN_GPIO1_6((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_GPIO3_0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// gpio1_0 = *PIRQ, gpio1_1 = *E_INT, gpio1_2 = *EXP_INT, gpio1_3 = *I2C_INT
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER81) = MX31_PIN_GPIO1_0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_GPIO1_1((OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO))
-									| MX31_PIN_GPIO1_2((OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO))
-									| MX31_PIN_GPIO1_3((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
-
-// capture = GPIO2, compare = GPIO3, watchdog_rst = NC, pwm0 = LCD_BKL
-IOMUX_CTL_REG(SW_MUX_CTL_REGISTER82) = MX31_PIN_CAPTURE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_COMPARE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_WATCHDOG_RST((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
-									| MX31_PIN_PWMO((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
-}
diff --git a/ports/beagleboneblack/omap3530_iomux.h b/ports/beagleboneblack/omap3530_iomux.h
deleted file mode 100644
index f424664..0000000
--- a/ports/beagleboneblack/omap3530_iomux.h
+++ /dev/null
@@ -1,1077 +0,0 @@
-//==========================================================================
-//
-// mx31_gpio.h
-//
-// Author(s):    Luis Torrico, Cogent Computer Systems, Inc.
-// Contributors: 
-// Date:         05/02/2008
-// Description:  This file contains offsets and bit defines
-//				 for the MCIMX31 Software Multiplexor Control Register
-//
-
-#include "omap3530.h"
-#include "bits.h"
-
-// Base address for Software Multiplexor Control Register (SW_MUX_CTL).
-// The SW_MUX_CTL has 82 seperate registers each of which contains 4
-// seperate Control Signals.  So we have to write to a total of 328
-// different signals in order to set-up the MX31 to run on the Cogent platform.
-#define IOMUXC_BASE_ADDR        0x43FAC000
-#define IOMUX_CTL_REG(_x_)		*(vulong *)(IOMUXC_BASE_ADDR + _x_)
-
-#define GENERAL_REGISTER			0x008
-#define SW_MUX_CTL_REGISTER1	    0x00C	// Contains cspi3_miso, cspi3_sclk, sspi3_spi_rdy, and ttm_pad
-#define SW_MUX_CTL_REGISTER2        0x010	// Contains ata_reset_b, ce_control, clkss, and cspi3_mosi
-#define SW_MUX_CTL_REGISTER3        0x014	// Contains ata_cs1, ata_dior, ata_diow, and ata_dmack
-#define SW_MUX_CTL_REGISTER4        0x018	// Contains sd1_data1, sd1_data2, sd1_data3, and ata_cs0
-#define SW_MUX_CTL_REGISTER5        0x01C	// Contains d3_spl, sd1_cmd, sd1_clk, and sd1_data0
-#define SW_MUX_CTL_REGISTER6        0x020	// Contains vsync3, contrast, d3_rev, and d3_cls
-#define SW_MUX_CTL_REGISTER7        0x024	// Contains ser_rs, par_rs, write, and read
-#define SW_MUX_CTL_REGISTER8        0x028	// Contains sd_d_io, sd_d_clk, lcs0, and lcs1
-#define SW_MUX_CTL_REGISTER9        0x02C	// Contains hsync, fpshift, drdy0, and sd_d_i
-#define SW_MUX_CTL_REGISTER10       0x030	// Contains ld15, ld16, ld17, and vsync0
-#define SW_MUX_CTL_REGISTER11       0x034
-#define SW_MUX_CTL_REGISTER12       0x038
-#define SW_MUX_CTL_REGISTER13       0x03C
-#define SW_MUX_CTL_REGISTER14       0x040
-#define SW_MUX_CTL_REGISTER15       0x044
-#define SW_MUX_CTL_REGISTER16       0x048
-#define SW_MUX_CTL_REGISTER17       0x04C
-#define SW_MUX_CTL_REGISTER18       0x050
-#define SW_MUX_CTL_REGISTER19       0x054
-#define SW_MUX_CTL_REGISTER20       0x058
-#define SW_MUX_CTL_REGISTER21       0x05C
-#define SW_MUX_CTL_REGISTER22       0x060
-#define SW_MUX_CTL_REGISTER23       0x064
-#define SW_MUX_CTL_REGISTER24       0x068
-#define SW_MUX_CTL_REGISTER25       0x06C
-#define SW_MUX_CTL_REGISTER26       0x070
-#define SW_MUX_CTL_REGISTER27       0x074
-#define SW_MUX_CTL_REGISTER28       0x078
-#define SW_MUX_CTL_REGISTER29       0x07C
-#define SW_MUX_CTL_REGISTER30       0x080
-#define SW_MUX_CTL_REGISTER31       0x084
-#define SW_MUX_CTL_REGISTER32       0x088
-#define SW_MUX_CTL_REGISTER33       0x08C
-#define SW_MUX_CTL_REGISTER34       0x090
-#define SW_MUX_CTL_REGISTER35       0x094
-#define SW_MUX_CTL_REGISTER36       0x098
-#define SW_MUX_CTL_REGISTER37       0x09C
-#define SW_MUX_CTL_REGISTER38       0x0A0
-#define SW_MUX_CTL_REGISTER39       0x0A4
-#define SW_MUX_CTL_REGISTER40       0x0A8
-#define SW_MUX_CTL_REGISTER41       0x0AC
-#define SW_MUX_CTL_REGISTER42       0x0B0
-#define SW_MUX_CTL_REGISTER43       0x0B4
-#define SW_MUX_CTL_REGISTER44       0x0B8
-#define SW_MUX_CTL_REGISTER45       0x0BC
-#define SW_MUX_CTL_REGISTER46       0x0C0
-#define SW_MUX_CTL_REGISTER47       0x0C4
-#define SW_MUX_CTL_REGISTER48       0x0C8
-#define SW_MUX_CTL_REGISTER49       0x0CC
-#define SW_MUX_CTL_REGISTER50       0x0D0
-#define SW_MUX_CTL_REGISTER51       0x0D4
-#define SW_MUX_CTL_REGISTER52       0x0D8
-#define SW_MUX_CTL_REGISTER53       0x0DC
-#define SW_MUX_CTL_REGISTER54       0x0E0
-#define SW_MUX_CTL_REGISTER55       0x0E4
-#define SW_MUX_CTL_REGISTER56       0x0E8
-#define SW_MUX_CTL_REGISTER57       0x0EC
-#define SW_MUX_CTL_REGISTER58       0x0F0
-#define SW_MUX_CTL_REGISTER59       0x0F4
-#define SW_MUX_CTL_REGISTER60       0x0F8
-#define SW_MUX_CTL_REGISTER61       0x0FC
-#define SW_MUX_CTL_REGISTER62       0x100
-#define SW_MUX_CTL_REGISTER63       0x104
-#define SW_MUX_CTL_REGISTER64       0x108
-#define SW_MUX_CTL_REGISTER65       0x10C
-#define SW_MUX_CTL_REGISTER66       0x110
-#define SW_MUX_CTL_REGISTER67       0x114
-#define SW_MUX_CTL_REGISTER68       0x118
-#define SW_MUX_CTL_REGISTER69       0x11C
-#define SW_MUX_CTL_REGISTER70       0x120
-#define SW_MUX_CTL_REGISTER71       0x124
-#define SW_MUX_CTL_REGISTER72       0x128
-#define SW_MUX_CTL_REGISTER73       0x12C
-#define SW_MUX_CTL_REGISTER74       0x130
-#define SW_MUX_CTL_REGISTER75       0x134
-#define SW_MUX_CTL_REGISTER76       0x138
-#define SW_MUX_CTL_REGISTER77       0x13C
-#define SW_MUX_CTL_REGISTER78       0x140
-#define SW_MUX_CTL_REGISTER79       0x144
-#define SW_MUX_CTL_REGISTER80       0x148
-#define SW_MUX_CTL_REGISTER81       0x14C
-#define SW_MUX_CTL_REGISTER82       0x150
-
-// General Purpose Register Bit Defines
-#define DDR_MODE_ON_CLK0_EN		BIT31		// 1 = Enable DDR mode on CLK0 contact
-#define USBH2_LOOPBACK_EN		BIT30		// 1 = Turn on sw_input_on (loopback) on some USBH2 contacts
-#define USBH1_LOOPBACK_EN		BIT29		// 1 = Turn on sw_input_on (loopback) on some USBH1 contacts
-#define USBOTG_LOOPBACK_EN		BIT28		// 1 = Turn on sw_input_on (loopback) on some USBOTG contacts
-#define USBH1_SUS_ON_SFS6_EN	BIT27		// 1 = Enable USBH1_SUSPEND signal on SFS6 contact
-#define ATA_ON_KEYPAD_EN		BIT26		// 1 = Enable ATA signals on Keypad Group contacts
-#define UART5_DMA_REQ_EN		BIT25		// Selects either CSPI3 or UART5 DMA requests for events 10 and 11, 1 = UART5, 0 = CSPI1
-#define	SLEW_RATE_SEL			BIT24		// 1 = Fast Slew Rate, 0 = Slow Slew Rate
-#define DRIVE_STRENGTH_SEL		BIT23		// 1 = Maximum drive strength, 0 = standard or high drive strength
-#define UPLL_ON_GPIO3_1_EN		BIT22		// 1 = Enable UPLL clock bypass through GPIO3_1 contact
-#define SPLL_ON_GPIO3_0_EN		BIT21		// 1 = Enable SPLL clock bypass through GPIO3_0 contact
-#define MSHC2_DMA_REQ_EN		BIT20		// Selects either SDHC2 or MSHC2 DMA requests, 1 = MSCHC2, 0 = SDHC2
-#define MSHC1_DMA_REQ_EN		BIT19		// Selects either SDHC1 or MSHC1 DMA requests, 1 = MSCHC1, 0 = SDHC1
-#define OTG_DATA_ON_UART_EN		BIT18		// 1 = Enable USBOTG_DATA[5:3] on Full UART Group contacts
-#define OTG_D4_ON_DSR_DCE1_EN	BIT17		// 1 = Enable USBOTG_DATA4 on DSR_DCE1 contact
-#define TAMPER_DETECT_EN		BIT16		// 1 = Enable Tamper detect logic
-#define MBX_DMA_REQ_EN			BIT15		// Selects either External or MBX DMA requests, 1 = MDX, 0 = External
-#define UART_DMA_REQ_EN			BIT14		// Selects either CSPI1 or UART3 DMA requests, 1 = UART3, 0 = CSPI1
-#define WEIM_ON_CS3_EN			BIT13		// Selects either CSD1 or WEIM on EMI CS3 contact, 1 = CSD1, 0 = WEIM
-#define WEIM_ON_CS2_EN			BIT12		// Selects either CSD0 or WEIM on EMI CS2 contact, 1 = CSD0, 0 = WEIM
-#define USBH2_ON_AUDIO_EN		BIT11		// 1 = Enable USBH2 signals on AudioPort 3 and AudioPort6
-#define ATA_SIG_ON_CSPI1_EN		BIT10		// 1 = Enable ATA signals on CSPI1 Group contacts
-#define ATA_DATA_ON_CSPI1_EN	BIT9		// 1 = Enable ATA DATA14-15 on Timer Group contacts and DATA0-6 on CSPI1 Group contacts
-#define ATA_DATA_ON_AUDIO_EN	BIT8		// 1 = Enable DATA7-10 signals of ATA on AudioPort3 and DATA11-13 on AudioPort6
-#define ATA_DATA_ON_IPU_EN		BIT7		// 1 = Enable DATA0-13 signals of ATA on IPU (CSI) and DATA14-15 on I2C
-#define ATA_SIG_ON_NANDF_EN		BIT6		// 1 = Enable ATA signals on NANF contacts
-#define ATA_DATA_ON_NANDF_EN	BIT5		// 1 = Enable ATA DATA7-13 on NANDF contacts
-#define ATA_ON_USBH2_EN			BIT4		// 1 = Enable ATA signals on USBH2 contacts
-#define PWMO_ON_ATA_IORDY_EN	BIT3		// 1 = Enable ATA IORDY signal on PWMO contact
-#define CSPI1_ON_UART_EN		BIT2		// 1 = Replaces Full UART Group with CSPI1 signals
-#define DDR_MODE_EN				BIT1		// 1 = Forces DDR type I/O contacts to DDR mode
-#define FIR_DMA_REQ_EN			BIT0		// Selects FIR or UART2 SDMA events, 1 = FIR, 0 = UART2
-
-// Initialization of GPR for CSB733
-//IOMUX_CTL_REG(GENERAL_REGISTER) = WEIM_ON_CS3_EN | CSPI1_ON_UART_EN;
-
-// various IOMUX output functions
-#define	OUTPUTCONFIG_GPIO	0x00	// used as GPIO
-#define	OUTPUTCONFIG_FUNC	0x10	// output used as function
-#define	OUTPUTCONFIG_ALT1	0x20	// output used as alternate function 1
-#define	OUTPUTCONFIG_ALT2	0x30	// output used as alternate function 2
-#define	OUTPUTCONFIG_ALT3	0x40	// output used as alternate function 3
-#define	OUTPUTCONFIG_ALT4	0x50	// output used as alternate function 4
-#define	OUTPUTCONFIG_ALT5	0x60	// output used as alternate function 5
-#define	OUTPUTCONFIG_ALT6	0x70	// output used as alternate function 6
-
-// various IOMUX input functions
-#define	INPUTCONFIG_NONE	0x00	// not configured for input
-#define	INPUTCONFIG_GPIO	0x01	// input used as GPIO
-#define	INPUTCONFIG_FUNC	0x02	// input used as function
-#define	INPUTCONFIG_ALT1	0x04	// input used as alternate function 1
-#define	INPUTCONFIG_ALT2	0x08	// input used as alternate function 2
-
-// Software Mux Control Signal Defines (SW_MUX_CTL_SIGNAL 1-4)
-#define	MX31_PIN_CSPI3_MISO(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_CSPI3_SCLK(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_CSPI3_SPI_RDY(_x_)	((_x_ & 0xff) << 8)
-#define	MX31_PIN_TTM_PAD(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_ATA_RESET_B(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_CE_CONTROL(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_CLKSS(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_CSPI3_MOSI(_x_)	((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_ATA_CS1(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_ATA_DIOR(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_ATA_DIOW(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_ATA_DMACK(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD1_DATA1(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD1_DATA2(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD1_DATA3(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_ATA_CS0(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_D3_SPL(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD1_CMD(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD1_CLK(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD1_DATA0(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_VSYNC3(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_CONTRAST(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_D3_REV(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_D3_CLS(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SER_RS(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_PAR_RS(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_WRITE(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_READ(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD_D_IO(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD_D_CLK(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_LCS0(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_LCS1(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_HSYNC(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_FPSHIFT(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_DRDY0(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD_D_I(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_LD15(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_LD16(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_LD17(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_VSYNC0(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_LD11(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_LD12(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_LD13(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_LD14(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_LD7(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_LD8(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_LD9(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_LD10(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_LD3(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_LD4(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_LD5(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_LD6(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_USBH2_DATA1(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_LD0(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_LD1(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_LD2(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_USBH2_DIR(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_USBH2_STP(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_USBH2_NXT(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_USBH2_DATA0(_x_)	((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_USBOTG_DATA5(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_USBOTG_DATA6(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_USBOTG_DATA7(_x_)	((_x_ & 0xff) << 8)
-#define	MX31_PIN_USBH2_CLK(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_USBOTG_DATA1(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_USBOTG_DATA2(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_USBOTG_DATA3(_x_)	((_x_ & 0xff) << 8)
-#define	MX31_PIN_USBOTG_DATA4(_x_)	((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_USBOTG_DIR(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_USBOTG_STP(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_USBOTG_NXT(_x_)	((_x_ & 0xff) << 8)
-#define	MX31_PIN_USBOTG_DATA0(_x_)	((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_USB_PWR(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_USB_OC(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_USB_BYP(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_USBOTG_CLK(_x_)	((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_TDO(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_TRSTB(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_DE_B(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SJC_MOD(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_RTCK(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_TCK(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_TMS(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_TDI(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_KEY_COL4(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_KEY_COL5(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_KEY_COL6(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_KEY_COL7(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_KEY_COL0(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_KEY_COL1(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_KEY_COL2(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_KEY_COL3(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_KEY_ROW4(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_KEY_ROW5(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_KEY_ROW6(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_KEY_ROW7(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_KEY_ROW0(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_KEY_ROW1(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_KEY_ROW2(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_KEY_ROW3(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_TXD2(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_RTS2(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_CTS2(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_BATT_LINE(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_RI_DTE1(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_DCD_DTE1(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_DTR_DCE2(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_RXD2(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_RI_DCE1(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_DCD_DCE1(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_DTR_DTE1(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_DSR_DTE1(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_RTS1(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_CTS1(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_DTR_DCE1(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_DSR_DCE1(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CSPI2_SCLK(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_CSPI2_SPI_RDY(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_RXD1(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_TXD1(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CSPI2_MISO(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_CSPI2_SS0(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_CSPI2_SS1(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_CSPI2_SS2(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CSPI1_SS2(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_CSPI1_SCLK(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_CSPI1_SPI_RDY(_x_)	((_x_ & 0xff) << 8)
-#define	MX31_PIN_CSPI2_MOSI(_x_)	((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CSPI1_MOSI(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_CSPI1_MISO(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_CSPI1_SS0(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_CSPI1_SS1(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_STXD6(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SRXD6(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SCK6(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SFS6(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_STXD5(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SRXD5(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SCK5(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SFS5(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_STXD4(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SRXD4(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SCK4(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SFS4(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_STXD3(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SRXD3(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SCK3(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SFS3(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CSI_HSYNC(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_CSI_PIXCLK(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_I2C_CLK(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_I2C_DAT(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CSI_D14(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_CSI_D15(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_CSI_MCLK(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_CSI_VSYNC(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CSI_D10(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_CSI_D11(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_CSI_D12(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_CSI_D13(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CSI_D6(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_CSI_D7(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_CSI_D8(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_CSI_D9(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_M_REQUEST(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_M_GRANT(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_CSI_D4(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_CSI_D5(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_PC_RST(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_IOIS16(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_PC_RW_B(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_PC_POE(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_PC_VS1(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_PC_VS2(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_PC_BVD1(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_PC_BVD2(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_PC_CD2_B(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_PC_WAIT_B(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_PC_READY(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_PC_PWRON(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_D2(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_D1(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_D0(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_PC_CD1_B(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_D6(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_D5(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_D4(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_D3(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_D10(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_D9(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_D8(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_D7(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_D14(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_D13(_x_)			((_x_ & 0xff) << 16)			
-#define	MX31_PIN_D12(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_D11(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_NFWP_B(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_NFCE_B(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_NFRB(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_D15(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_NFWE_B(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_NFRE_B(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_NFALE(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_NFCLE(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SDQS0(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SDQS1(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SDQS2(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SDQS3(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SDCKE0(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_SDCKE1(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_SDCLK(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SDCLK_B(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_RW(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_RAS(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_CAS(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SDWE(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CS5(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_ECB(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_LBA(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_BCLK(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CS1(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_CS2(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_CS3(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_CS4(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_EB0(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_EB1(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_OE(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_CS0(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_DQM0(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_DQM1(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_DQM2(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_DQM3(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD28(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD29(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD30(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD31(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD24(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD25(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD26(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD27(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD20(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD21(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD22(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD23(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD16(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD17(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD18(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD19(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD12(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD13(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD14(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD15(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD8(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD9(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD10(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD11(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD4(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD5(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD6(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD7(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_SD0(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SD1(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SD2(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SD3(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_A24(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_A25(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SDBA1(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SDBA0(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_A20(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_A21(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_A22(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_A23(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_A16(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_A17(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_A18(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_A19(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_A12(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_A13(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_A14(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_A15(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_A9(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_A10(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_MA10(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_A11(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_A5(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_A6(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_A7(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_A8(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_A1(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_A2(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_A3(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_A4(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_DVFS1(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_VPG0(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_VPG1(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_A0(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CKIL(_x_)			((_x_ & 0xff) << 24)
-#define MX31_PIN_POWER_FAIL(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_VSTBY(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_DVFS0(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_BOOT_MODE1(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_BOOT_MODE2(_x_)	((_x_ & 0xff) << 16)
-#define	MX31_PIN_BOOT_MODE3(_x_)	((_x_ & 0xff) << 8)
-#define	MX31_PIN_BOOT_MODE4(_x_)	((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_RESET_IN_B(_x_)	((_x_ & 0xff) << 24)
-#define	MX31_PIN_POR_B(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_CLKO(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_BOOT_MODE0(_x_)	((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_STX0(_x_)			((_x_ & 0xff) << 24)
-#define	MX31_PIN_SRX0(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SIMPD0(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_CKIH(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_GPIO3_1(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_SCLK0(_x_)			((_x_ & 0xff) << 16)
-#define	MX31_PIN_SRST0(_x_)			((_x_ & 0xff) << 8)
-#define	MX31_PIN_SVEN0(_x_)			((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_GPIO1_4(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_GPIO1_5(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_GPIO1_6(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_GPIO3_0(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_GPIO1_0(_x_)		((_x_ & 0xff) << 24)
-#define	MX31_PIN_GPIO1_1(_x_)		((_x_ & 0xff) << 16)
-#define	MX31_PIN_GPIO1_2(_x_)		((_x_ & 0xff) << 8)
-#define	MX31_PIN_GPIO1_3(_x_)		((_x_ & 0xff) << 0)
-
-#define	MX31_PIN_CAPTURE(_x_)		 ((_x_ & 0xff) << 24)
-#define	MX31_PIN_COMPARE(_x_)		 ((_x_ & 0xff) << 16)
-#define	MX31_PIN_WATCHDOG_RST(_x_)	 ((_x_ & 0xff) << 8)
-#define	MX31_PIN_PWMO(_x_)			 ((_x_ & 0xff) << 0)
-
-//// MX31_PIN_TTM_PAD = can not be written to.
-//// cspi_miso = U2_RXD, cspi3_sclk = U2_RTS, cspi3_spi_rdy = U2_CTS, ttm_pad = default
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER1) = MX31_PIN_CSPI3_MISO(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
-//									| MX31_PIN_CSPI3_SCLK(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
-//									| MX31_PIN_CSPI3_SPI_RDY(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
-//									| MX31_PIN_TTM_PAD();
-//
-//// MX31_PIN_CLKSS and MX31_PIN_CE_CONTROL = can not be written to.
-//// reset_b = NC, ce_control = default, ctl_clkss = default, cspi3_mosi = U2_RXD
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER2) = MX31_PIN_ATA_RESET_B(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_CE_CONTROL(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CLKSS()
-//									| MX31_PIN_CSPI3_MOSI(OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT2);
-//
-//// ata_cs1 = NC, ata_dior = D_TXD, ata_diow = NC, ata, dmack = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER3) = MX31_PIN_ATA_CS1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_ATA_DIOR(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
-//									| MX31_PIN_ATA_DIOW(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_ATA_DMACK(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// sd1_data1 = SD_D1, sd1_data2 = SD_D2, sd1_data3 = SD_D3, ata_cs0 = D_RXD
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER4) = MX31_PIN_SD1_DATA1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SD1_DATA2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SD1_DATA3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_ATA_CS0(OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1);
-//
-//// d3_spl = NC, sd1_cmd = SD_CMD, sd1_clk - SD_CLK, sd1_data0 = SD_D0
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER5) = MX31_PIN_D3_SPL(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_SD1_CMD(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SD1_CLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_SD1_DATA0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// vsync3 = LCD_VSYNC, contrast = NC, d3_rev = NC, d3_cls = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER6) = MX31_PIN_VSYNC3(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_CONTRAST(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_D3_REV(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_D3_CLS(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
-//
-//// ser_rs = NC, par_rs = NC, write = NC, read = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER7) = MX31_PIN_SER_RS(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_PAR_RS(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_WRITE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_READ(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// sd_d_io = NC, sd_d_clk = NC, lcs0 = NC, lcs1 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER8) = MX31_PIN_SD_D_IO(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_SD_D_CLK(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_LCS0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_LCS1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// hsync = LCD_HSYNC, fpshift = LCD_PCLK, drdy0 = LCD_OE, sd_d_i = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER9) = MX31_PIN_HSYNC(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_FPSHIFT(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_DRDY0(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_SD_D_I(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// ld15 = LCD_R3, ld16 = LCD_R4, ld17 = LCD_R5, sd_d_i = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER10) = MX31_PIN_LD15(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD16(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD17(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_VSYNC0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// ld11 = LCD_G5, ld12 = LCD_R0, ld13 = LCD_R1, ld14 = LCD_R2
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER11) = MX31_PIN_LD11(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD12(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD13(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD14(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// ld7 = LCD_G1, ld8 = LCD_G2, ld9 = LCD_G3, ld10 = LCD_G4
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER12) = MX31_PIN_LD7(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD8(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD9(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD10(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// ld3 = LCD_B3, ld4 = LCD_B4, ld5 = LCD_B5, ld6 = LCD_G0
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER13) = MX31_PIN_LD3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD4(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// usbh2_data1 = UH2_D1, ld0 = LCD_B0, ld1 = LCD_B1, ld2 = LCD_B0
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER14) = MX31_PIN_USBH2_DATA1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_LD2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// usbh2_dir = UH2_DIR, usbh2_stp = UH2_STP, usbh2_nxt = UH2_NXT, usbh2_data0 = UH2_D0
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER15) = MX31_PIN_USBH2_DIR(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_USBH2_STP(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBH2_NXT(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBH2_DATA0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// usbotg_data5 = UD_D5, usbotg_data6 = UD_D6, usbotg_data7 = UD_D7, usbh2_clk = UH2_CLK
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER16) = MX31_PIN_USBOTG_DATA5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBOTG_DATA6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBOTG_DATA7(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBH2_CLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// usbotg_data1 = UD_D1, usbotg_data2 = UD_D2, usbotg_data3 = UD_D3, usbotg_data4 = UD_D4
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER17) = MX31_PIN_USBOTG_DATA1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBOTG_DATA2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBOTG_DATA3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBOTG_DATA4(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// usbotg_dir = UD_DIR, usbotg_stp = UD_STP, usbotg_nxt = UD_NXT, usbotg_data0 = UD_D0
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER18) = MX31_PIN_USBOTG_DIR(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBOTG_STP(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_USBOTG_NXT(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_USBOTG_DATA0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// usb_pwr = NC, usb_oc = CF_RST, usb_byp = NC, usbotg_clk = UD_CLK
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER19) = MX31_PIN_USB_PWR(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_USB_OC(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_USB_BYP(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_USBOTG_CLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// MX31_PIN_TDO and MX31_PIN_SJC_MOD = can not be written to
-//// tdo = TDO_C, trstb = TRST_C, de_b = TP1, sjc_mod = GND
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER20) = MX31_PIN_TDO()
-//									| MX31_PIN_TRSTB(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_DE_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SJC_MOD();
-//
-//// MX31_PIN_RTCK = can not be written to.
-//// rtck = NC, tck = TCK_C, tms = TMS_C, tdi = TDI_C
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER21) = MX31_PIN_RTCK()
-//									| MX31_PIN_TCK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_TMS(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_TDI(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// key_col4 = NC, key_col5 = NC, key_col6 = NC, key_col7 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER22) = MX31_PIN_KEY_COL4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_KEY_COL5(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_KEY_COL6(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_KEY_COL7(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// key_col0 = NC, key_col1 = NC, key_col2 = NC, key_col3 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER23) = MX31_PIN_KEY_COL0(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_KEY_COL1(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_KEY_COL2(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_KEY_COL3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
-//
-//// key_row4 = NC, key_row5 = NC, key_row6 = NC, key_row7 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER24) = MX31_PIN_KEY_ROW4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_KEY_ROW5(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_KEY_ROW6(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_KEY_ROW7(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// key_row0 = NC, key_row1 = NC, key_row2 = NC, key_row3 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER25) = MX31_PIN_KEY_ROW0(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_KEY_ROW1(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_KEY_ROW2(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_KEY_ROW3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
-//
-//// txd2 = U1_TXD, rts2 = U1_RTS, cts2 = U1_CTS, batt_line = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER26) = MX31_PIN_TXD2(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_RTS2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CTS2(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_BATT_LINE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// ri_dte1, dcd_dte1, and dtr_dce2 are set to CSPI1 signals by GPR(2)
-//// rxd2 = U1_RXD
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER27) = MX31_PIN_RI_DTE1()
-//									| MX31_PIN_DCD_DTE1()
-//									| MX31_PIN_DTR_DCE2()
-//									| MX31_PIN_RXD2(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC);
-//
-//// dtr_dte1 and dsr_dte1 are set to CSPI1 signals by GPR(2)
-//// ri_dce1 = SPI0_RDY, dcd_dce1 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER28) = MX31_PIN_RI_DCE1(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
-//									| MX31_PIN_DCD_DCE1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_DTR_DTE1()
-//									| MX31_PIN_DSR_DTE1();
-//
-//// rts1 = U0_RTS, cts1 = U0_CTS, dtr_dce1 = NC, dsr_dce1 = SPI0_CLK
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER29) = MX31_PIN_RTS1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CTS1(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_DTR_DCE1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_DSR_DCE1(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1);
-//
-//// cspi2_sclk = SPI1_CLK, cspi2_spi_rdy = SPI1_RDY, rxd1 = U0_RXD, txd1 = U0_TXD
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER30) = MX31_PIN_CSPI2_SCLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSPI2_SPI_RDY(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_RXD1(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)
-//									| MX31_PIN_TXD1(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE);
-//
-//// cspi2_miso = SPI1_MISO, cspi2_ss0 = SPI1_CS0, cspi2_ss1 = SPI1_CS1, cspi2_ss2 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER31) = MX31_PIN_CSPI2_MISO(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSPI2_SS0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSPI2_SS1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSPI2_SS2(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
-//
-//// cspi1_ss2 = UH1_RCV, cspi1_sclk = UH1_OE, cspi1_spi_rdy = UH1_FS, cspi2_mosi = SPI1_MOSI
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER32) = MX31_PIN_CSPI1_SS2(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
-//									| MX31_PIN_CSPI1_SCLK(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
-//									| MX31_PIN_CSPI1_SPI_RDY(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
-//									| MX31_PIN_CSPI2_MOSI(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// cspi1_mosi = UH1_RXDM, cspi1_miso = UH1_RXDP, cspi1_ss0 = UH1_TXDM, cspi1_ss1 = UH1_TXDP
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER33) = MX31_PIN_CSPI1_MOSI(OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1)
-//									| MX31_PIN_CSPI1_MISO(OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1)
-//									| MX31_PIN_CSPI1_SS0(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
-//									| MX31_PIN_CSPI1_SS1(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE);
-//
-//// stxd6 = AC_SDOUT, srxd6 = AC_SDIN, sck6 = AC_BCLK, sfs6 = AC_SYNC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER34) = MX31_PIN_STXD6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SRXD6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SCK6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SFS6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// stxd5 = SSI_TXD, srxd5 = SSI_RXD, sck5 = SSI_CLK, sfs5 = SSI_FRM
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER35) = MX31_PIN_STXD5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SRXD5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SCK5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SFS5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// stxd4 = NC, srxd4 = NC, sck4 = SSI_MCLK, sfs4 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER36) = MX31_PIN_STXD4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_SRXD4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_SCK4(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SFS4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// stxd3 = AC_RST, srxd3 = NC, sck3 = NC, sfs3 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER37) = MX31_PIN_STXD3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_SRXD3(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_SCK3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_SFS3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
-//
-//// csi_hsync = VIP_HSYNC, csi_pixclk = VIP_PCLK, i2c_clk = I2C_SCL, i2c_dat = I2C_SDA
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER38) = MX31_PIN_CSI_HSYNC(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_PIXCLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_I2C_CLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_I2C_DAT(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// csi_d14 = VIP_D8, csi_d15 = VIP_D9, csi_mclk = VIP_MCLK, csi_vsync = VIP_VSYNC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER39) = MX31_PIN_CSI_D14(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_D15(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_MCLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
-//									| MX31_PIN_CSI_VSYNC(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// csi_d10 = VIP_D4, csi_d11 = VIP_D5, csi_D12 = VIP_D6, csi_D13 = VIP_D7
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER40) = MX31_PIN_CSI_D10(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_D11(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_D12(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_D13(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// csi_d6 = VIP_D0, csi_d7 = VIP_D1, csi_D8 = VIP_D2, csi_D9 = VIP_D3
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER41) = MX31_PIN_CSI_D6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_D7(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_D8(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_D9(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// m_request = NC, m_grant = NC, csi_d4 = NC, csi_d5 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER42) = MX31_PIN_M_REQUEST(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_M_GRANT(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CSI_D4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_CSI_D5(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// pc_rst = UH2_D5, isis16 = UH2_D6, pc_rw_b = UH2_D7, pc_poe = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER43) = MX31_PIN_PC_RST(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
-//									| MX31_PIN_IOIS16(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
-//									| MX31_PIN_PC_RW_B(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
-//									| MX31_PIN_PC_POE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// pc_vs1 = NC, pc_vs2 = UH2_D2, pc_bvd1 = UH2_D3, pc_bvd2 = UH2_D4
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER44) = MX31_PIN_PC_VS1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_PC_VS2(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
-//									| MX31_PIN_PC_BVD1(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
-//									| MX31_PIN_PC_BVD2(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1);
-//
-//// pc_cd2_b = CF_CD, pc_wait_b = CF_WAIT, pc_ready = CF_RDY, pc_pwron = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER45) = MX31_PIN_PC_CD2_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_PC_WAIT_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_PC_READY(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_PC_PWRON(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// d2, d1, and d0 are not writable, reset values are correct.
-//// d2 = LD2, d1 = LD1, d0 = LD0, pc_cd1_b = CF_CD
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER46) = MX31_PIN_D2()
-//									| MX31_PIN_D1()
-//									| MX31_PIN_D0()
-//									| MX31_PIN_PC_CD1_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// d6, d5, d4 and d3 are not writable, reset values are correct.
-//// d6 = LD6, d5 = LD5, d4 = LD4, d3 = LD3
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER47) = MX31_PIN_D6()
-//									| MX31_PIN_D5()
-//									| MX31_PIN_D4()
-//									| MX31_PIN_D3();
-//
-//// d10, d9, d8 and d7 are not writable, reset values are correct.
-//// d10 = LD10, d9 = LD9, d8 = LD8, d7 = LD7
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER48) = MX31_PIN_D10()
-//									| MX31_PIN_D9()
-//									| MX31_PIN_D8()
-//									| MX31_PIN_D7();
-//
-//// d14, d13, d12 and d11 are not writable, reset values are correct.
-//// d14 = LD14, d13 = LD13, d12 = LD12, d11 = L11
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER49) = MX31_PIN_D14()
-//									| MX31_PIN_D13()
-//									| MX31_PIN_D12()
-//									| MX31_PIN_D11();
-//
-//// d15 is not writable, reset value is correct.
-//// nfwp_b = *N_WP, nfce_b = *N_CE, nfrb = N_RDY, d15 = LD15
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER50) = MX31_PIN_NFWP_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_NFCE_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_NFRB(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_D15();
-//
-//// nfwe_b = *N_WE, nfre_b = *N_RE, nfale = N_ALE, nfcle = N_CLE
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER51) = MX31_PIN_NFWE_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_NFRE_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_NFALE(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_NFCLE(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// sdqs0, sdqs1, sdqs2, and sdqs3 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER52) = MX31_PIN_SDQS0()
-//									| MX31_PIN_SDQS1()
-//									| MX31_PIN_SDQS2()
-//									| MX31_PIN_SDQS3();
-//
-//// sdclk_b is not writable, reset value is correct.
-//// sdcke0 = SDCKE, sdcke1 = NC, sdclk = SDCLK, sdclk_b = *SDCLK
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER53) = MX31_PIN_SDCKE0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SDCKE1(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SDCLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SDCLK_B();
-//
-//// rw = *WE, ras = *SDRAS, cas = *SDCAS, sdwe = *SDWE
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER54) = MX31_PIN_RW(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_RAS(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CAS(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SDWE(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// ecb is not writable, reset value is correct.
-//// cs5 = *CS5, ecb = ECB, lba = LBA, bclk = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER55) = MX31_PIN_CS5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_ECB()
-//									| MX31_PIN_LBA(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_BCLK(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// cs1 = *CS1, cs2 = *SDCS, cs3 = NC, cs4 = *DTACK
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER56) = MX31_PIN_CS1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CS2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CS3(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_CS4(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1);
-//
-//// eb0 = *BE0, eb1 = *BE1, oe = *OE, cs0 = *CS0
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER57) = MX31_PIN_EB0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_EB1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_OE(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_CS0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// dqm0 = DQM0, dqm1 = DQM1, dqm2 = DQM2, dqm3 = DQM3
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER58) = MX31_PIN_DQM0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_DQM1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_DQM2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_DQM3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// sd28, sd29, sd30 and sd31 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER59) = MX31_PIN_SD28()
-//									| MX31_PIN_SD29()
-//									| MX31_PIN_SD30()
-//									| MX31_PIN_SD31();
-//
-//// sd24, sd25, sd26 and sd27 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER60) = MX31_PIN_SD24()
-//									| MX31_PIN_SD25()
-//									| MX31_PIN_SD26()
-//									| MX31_PIN_SD27();
-//
-//// sd20, sd21, sd22 and sd23 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER61) = MX31_PIN_SD20()
-//									| MX31_PIN_SD21()
-//									| MX31_PIN_SD22()
-//									| MX31_PIN_SD23();
-//
-//// sd16, sd17, sd18 and sd19 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER62) = MX31_PIN_SD16()
-//									| MX31_PIN_SD17()
-//									| MX31_PIN_SD18()
-//									| MX31_PIN_SD19();
-//
-//// sd12, sd13, sd14 and sd15 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER63) = MX31_PIN_SD12()
-//									| MX31_PIN_SD13()
-//									| MX31_PIN_SD14()
-//									| MX31_PIN_SD15();
-//
-//// sd8, sd9, sd10 and sd11 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER64) = MX31_PIN_SD8()
-//									| MX31_PIN_SD9()
-//									| MX31_PIN_SD10()
-//									| MX31_PIN_SD11();
-//
-//// sd4, sd5, sd6 and sd7 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER65) = MX31_PIN_SD4()
-//									| MX31_PIN_SD5()
-//									| MX31_PIN_SD6()
-//									| MX31_PIN_SD7();
-//
-//// sd0, sd1, sd2 and sd3 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER66) = MX31_PIN_SD0()
-//									| MX31_PIN_SD1()
-//									| MX31_PIN_SD2()
-//									| MX31_PIN_SD3();
-//
-//// a24 = A24, a25 = A25, sdba1 = SDBA1, sdba0 = SDBA0
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER67) = MX31_PIN_A24(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A25(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SDBA1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_SDBA0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// address lines are one to one.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER68) = MX31_PIN_A20(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A21(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A22(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A23(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// address lines are one to one.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER69) = MX31_PIN_A16(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A17(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A18(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A19(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// address lines are one to one.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER70) = MX31_PIN_A12(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A13(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A14(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A15(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// address lines are one to one.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER71) = MX31_PIN_A9(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A10(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_MA10(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A11(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// address lines are one to one.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER72) = MX31_PIN_A5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A7(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A8(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// address lines are one to one.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER73) = MX31_PIN_A1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_A4(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// dvfs1 = NC, vpg0 = NC, vpg1 = NC, a0 = A0
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER74) = MX31_PIN_DVFS1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_VPG0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_VPG1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_A0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
-//
-//// ckil and power_fail are not writable, reset values are correct.
-////ckil = 32K, power_fail = PWR_FAIL, vstby = VSTBY, dvfs0 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER75) = MX31_PIN_CKIL()
-//									| MX31_PIN_POWER_FAIL()
-//									| MX31_PIN_VSTBY(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_DVFS0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// boot_mode1, boot_mode2, boot_mode3, and boot_mode4 are not writable, reset values are correct.
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER76) = MX31_PIN_BOOT_MODE1()
-//									| MX31_PIN_BOOT_MODE2()
-//									| MX31_PIN_BOOT_MODE3()
-//									| MX31_PIN_BOOT_MODE4();
-//
-//// por_b, clko, and boot_mode0 are not writable, reset values are correct.
-//// reset_in_b = *RST_IN (this is set in the GPR)
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER77) = MX31_PIN_RESET_IN_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
-//									| MX31_PIN_POR_B()
-//									| MX31_PIN_CLKO()
-//									| MX31_PIN_BOOT_MODE0();
-//
-//// ckih is not writable, reset value is correct.
-//// stx0 = GPIO1, srx0 = GPIO4, simpd0 = GPIO5
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER78) = MX31_PIN_STX0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_SRX0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_SIMPD0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_CKIH();
-//
-//// gpio3_1 = VF_EN, sclk0 = GPIO8, srst0 = GPIO9, sven0 = GPIO0
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER79) = MX31_PIN_GPIO3_1(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
-//									| MX31_PIN_SCLK0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_SRST0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_SVEN0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// gpio1_4 = UH1_SUSP, gpio1_5 = PWR_RDY, gpio1_6 = UH1_MODE, gpio3_0 = NC
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER80) = MX31_PIN_GPIO1_4(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
-//									| MX31_PIN_GPIO1_5(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)
-//									| MX31_PIN_GPIO1_6(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_GPIO3_0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// gpio1_0 = *PIRQ, gpio1_1 = *E_INT, gpio1_2 = *EXP_INT, gpio1_3 = *I2C_INT
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER81) = MX31_PIN_GPIO1_0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_GPIO1_1(OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO)
-//									| MX31_PIN_GPIO1_2(OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO)
-//									| MX31_PIN_GPIO1_3(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
-//
-//// capture = GPIO2, compare = GPIO3, watchdog_rst = NC, pwm0 = LCD_BKL
-//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER82) = MX31_PIN_CAPTURE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_COMPARE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_WATCHDOG_RST(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
-//									| MX31_PIN_PWMO(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
diff --git a/ports/beagleboneblack/omap3530_lcd.c b/ports/beagleboneblack/omap3530_lcd.c
deleted file mode 100644
index 13a2c37..0000000
--- a/ports/beagleboneblack/omap3530_lcd.c
+++ /dev/null
@@ -1,342 +0,0 @@
-//==========================================================================
-//
-//      omap3530_lcd.c
-//
-// Author(s):   Luis Torrico - Cogent Computer Systems, Inc.
-// Date:        12-10-2008
-// Description:	Init Code for TI OMAP3530 LCD Controller
-// NOTE 		Only 16-bit mode has been tested!
-//
-//==========================================================================
-
-#include "config.h"
-#include "cpuio.h"
-#include "stddefs.h"
-#include "genlib.h"
-#include "omap3530.h"
-#include "omap3530_lcd.h"
-#include "cpu_gpio.h"
-#include "vga_lookup.h"
-#include "font8x16.h"
-#include "fb_draw.h"
-#include "warmstart.h"
-
-#if INCLUDE_LCD
-
-//--------------------------------------------------------------------------
-// function prototypes and externs
-//
-void fbdev_init(void);
-
-extern void udelay(int);
-extern int GPIO_clr(int);
-extern int GPIO_set(int);
-extern int GPIO_tst(int);
-extern int GPIO_out(int);
-extern int GPIO_in(int);
-
-// ADDED FOR WRITING CHARACTERS TO THE DISPLAY
-void lcd_putchar(char c);
-void lcd_writechar(uchar c);
-void lcd_clr_row(int char_row);
-void lcd_clr_scr(void);
-void lcd_switch_buffer(void);
-
-// globals to keep track of foreground, background colors and x,y position
-int lcd_color_depth;		// 4, 8 or 16
-int lcd_fg_color;			// 0 to 15, used as lookup into VGA color table
-int lcd_bg_color;			// 0 to 15, used as lookup into VGA color table
-int lcd_col;				// current column, 0 to COLS_PER_SCREEN - 1
-int lcd_row;				// current row, 0 to (ROWS_PER_SCREEN * 2) - 1
-int lcd_tst_mode = 0;
-ulong lcd_fb_offset;	   	// current offset into frame buffer for lcd_putchar
-
-//#define LCD_DBG
-//--------------------------------------------------------------------------
-// fbdev_init
-//
-// This function sets up the OMAP3530 LCD Controller, to be used
-// as uMon's frame buffer device.
-//
-void
-fbdev_init(void)
-{
-	//ushort temp16;
-
-	if (StateOfMonitor != INITIALIZE)
-		return;
-
-	lcd_color_depth = 16;
-	lcd_fg_color = vga_lookup[LCD_FG_DEF];
-	lcd_bg_color = vga_lookup[LCD_BG_DEF];
-
-	// Select DSS1_ALWON_FCLK (96MHz) as source for DSI and DISPC
-    DSS_REG(DSS_CONTROL) = 0x30;
-
-    // apply a soft reset to the display subsystem
-    DISPC_REG(DISPC_SYSCONFIG) = 0x02;
-
-	udelay(1000);
-	
-	// Set interface and functional clock to on during wakeup
-	// and no standby or idle
-    DISPC_REG(DISPC_SYSCONFIG) |= 0x2015;
-
-	// Set up the DMA base address
-    DISPC_REG(DISPC_GFX_BA) = 0x80200000;
- 
-	// Set up RGB 16 and disable the DMA for now
-    DISPC_REG(DISPC_GFX_ATTR) = 0x0000000C;
- 
-	// Set preload based on equation in section 15.5.3.2 in RM 
-    //DISPC_REG(DISPC_GFX_PRELOAD) = 0x60;
- 
-	// Set number of bytes to increment at end of row to 1 (default value) 
-    DISPC_REG(DISPC_GFX_ROW_INC) = 0x0001;
- 
-	// Set number of bytes to increment between two pixels to 1 (default value)
-    DISPC_REG(DISPC_GFX_PIX_INC) = 0x0001;
- 
-	// Set FIFO thresholds to defaults (hi = 1023, lo = 960)
-    //DISPC_REG(DISPC_GFX_FIFO_TH) = 0x03FF03C0;
-    DISPC_REG(DISPC_GFX_FIFO_TH) = 0x03FC03BC;
- 
-	// Set start position to 0 (frame buffer and active display area are the same)
-    DISPC_REG(DISPC_GFX_POS) = 0x00000000;
- 
-	// Set frame buffer size, Y = PIXELS_PER_COL, X = PIXELS_PER_ROW
-    DISPC_REG(DISPC_GFX_SIZE) = (((PIXELS_PER_COL -1) << 16) | (PIXELS_PER_ROW - 1));
- 
-	// Set the control register keep bit 5 (GOLCD) and bit 28 (LCDENABLESIGNAL) low
-	// until shadow registers have all been written
-    DISPC_REG(DISPC_CONTROL) = 0x38019209;
- 
-    // Disable all gating, pixel clock always toggles, frame data only
-	// loaded every frame (palette/gamma table off)
-    DISPC_REG(DISPC_CONFIG) = 0x00000004;
-    //DISPC_REG(DISPC_CONFIG) = 0x00000000;
- 
-    // Disable all capabilities not used for LCD
-    DISPC_REG(DISPC_CAPABLE) = 0x00000000;
- 
-	// Set horizontal timing
-    DISPC_REG(DISPC_TIMING_H) = ((LCD_H_BACK << 20) | (LCD_H_FRONT << 8) | LCD_H_WIDTH);
- 
-	// Set vertical timing
-    DISPC_REG(DISPC_TIMING_V) = ((LCD_V_BACK << 20) | (LCD_V_FRONT << 8) | LCD_V_WIDTH);
- 
-	// Set syncs low true and DE to hi true
-    DISPC_REG(DISPC_POL_FREQ) = 0x00003000;
-	
-	// Set logic divisor to 1 and pixel divisor to 2
-    DISPC_REG(DISPC_DIVISOR) = 0x00020001;
-	
-	// Set LCD size, lines per panel is , pixels per line is 
-    DISPC_REG(DISPC_SIZE_LCD) = (((PIXELS_PER_COL -1) << 16) | (PIXELS_PER_ROW - 1));
-	
-	// Enable the DMA
-    DISPC_REG(DISPC_GFX_ATTR) |= 0x00000001;
- 
-	// Set bit 5 (GOLCD) to enable LCD
-    DISPC_REG(DISPC_CONTROL) |= 0x00000020;
-
-	printf("OMAP3530 LCD Initialization Complete.\n");
-
-	return;
-}
-
-/* fbdev_setstart():
- * Used by uMon's FBI interface to establish the starting address of
- * the frame buffer memory.
- */
-void
-fbdev_setstart(long offset)
-{
-	// Select DSS1_ALWON_FCLK (96MHz) as source for DSI and DISPC
-    DSS_REG(DSS_CONTROL) = 0x30;
-
-    // Set up the DMA base address
-    DISPC_REG(DISPC_GFX_BA) = offset;
-
-	// Enable the DMA
-    DISPC_REG(DISPC_GFX_ATTR) |= 0x00000001;
- 
-	// Set bit 5 (GOLCD) to enable LCD
-    DISPC_REG(DISPC_CONTROL) |= 0x00000020;
-
-	return;
-}
-
-char *lcd_tstHelp[] = {
-    "OMAP3530 LCD controller test",
-    "-[n,x,d[4,8,16]]",
-	"The user may set color depth to run the test at.",
-	"The frame buffer R/W test will test all of the frame ",
-	"buffer regardless of depth.",
-    "Options...",
-    "  -n    run test without keycheck - CAUTION: RESET SYSTEM TO STOP!",
-	"  -d4   run test, force a depth of 4-bits/pixel",
-	"  -d8   run test, force a depth of 8-bits/pixel",
-	"  -d16  run test, force a depth of 16-bits/pixel",
-	"  -x    init only, do not run frame buffer tests",
-	"",
-	"  No options, default to current mode and depth.",
-	0
-};
-
-int lcd_tst(int argc,char *argv[])
-{
-	volatile ushort wr16, rd16;
-	int i, x, opt;
-	int no_wait = 0;
-	int init_only = 0;
-	char c;
-
-	lcd_tst_mode = 1;
-
-    while ((opt=getopt(argc,argv,"clnsxd:4,8,16")) != -1) {
-        switch(opt) {
-			case 'd':	// set the color depth
-                switch(*optarg) {
-            	    case '4':
-	        	        lcd_color_depth = 4;
-						printf("Forcing 4bpp Mode!\n");
-        	            break;
-    	            case '8':
-            	        lcd_color_depth = 8;
-						printf("Forcing 8bpp Mode!\n");
-                    	break;
-	                default:	// test with 16bpp
-	                    lcd_color_depth = 16;
-						printf("Forcing 16bpp Mode!\n");
-						break;
-                }
-	            break;
-	        case 'n':   // no waiting for keypress - fastest operation
-				no_wait = 1;
-				printf("No Keypress Mode, Must Reset System to Stop!\n");
-				break;
-	        case 'x':   // init only 
-				no_wait = 1;
-				printf("Initializing LCD, Skipping testsp!\n");
-				init_only = 1;
-				break;
-			default:	// test with current mode
-				break;
-		}
-	}
-
-	// get the new parameters into the LCD controller
-	fbdev_init();
-
-	if (init_only) return 0;
-
-	printf("Frame Buffer R/W...");
-	// do an address=data read/write test on the frame buffer
-	// PIXELS_PER_COL * PIXELS_PER_ROW is the highest pixel.  
-	// Multiply by bits_per_pixel (sed_color_depth), then
-	// divide by 8 to get the actual byte count.
-	for (i = 0; i < LCD_FB_SIZE(lcd_color_depth) + LCD_ROW_SIZE(lcd_color_depth); i += 2){	
-		LCD_BUF(i) = i & 0xffff;
-		rd16 = LCD_BUF(i);
-		if(rd16 != (i & 0xffff)){
-			printf("Fail at 0x%08x, WR 0x%08x, RD 0x%04lx!\n",LCD_BUF_ADD + i, i, (ulong)rd16);
-			return -1;
-		}
-	} 
-
-	printf("OK!, Press key to continue.\n");
-
-	c = getchar();
-
-	printf("Frame Buffer Start: 0x%08x, End 0x%08x\n",LCD_BUF_ADD, 
-			LCD_BUF_ADD + LCD_FB_SIZE(lcd_color_depth) + LCD_ROW_SIZE(lcd_color_depth));
-	if (no_wait)
-	{
-		printf("Begin Full Screen Color Test.\n");
-		while(1){
-			// fill the frame buffer with incrementing color values
-			for (x = 0; x < 16; x++){
-				switch (lcd_color_depth){
-					case 4:  wr16 = x | x << 4 | x << 8 | x << 12; break;
-					case 8:  wr16 = x | x << 8; break;
-					default: wr16 = vga_lookup[x]; break;	// 16-bits bypasses the lookup table
-				}
-				for (i = 0; i < LCD_FB_SIZE(lcd_color_depth); i += 2){	
-					LCD_BUF(i) = wr16;
-				}
-			} // for x
-		} // while
-	} // no_wait
-	else
-	{
-		printf("Begin Full Screen Color Test, Press any key to go to next color, \'x\' to end.\n");
-		while(1){
-			// fill the frame buffer with incrementing color values
-			for (x = 0; x < 16; x++){
-				switch (lcd_color_depth){
-					case 4:  wr16 = x | x << 4 | x << 8 | x << 12; break;
-					case 8:  wr16 = x | x << 8; break;
-					default: wr16 = vga_lookup[x]; break;	// 16-bits bypasses the lookup table
-				}
-				for (i = 0; i < LCD_FB_SIZE(lcd_color_depth) + LCD_ROW_SIZE(lcd_color_depth); i += 2){	
-					LCD_BUF(i) = wr16;
-				}
-				c = getchar();
-				if (c == 'x') goto lcd_tst_next;
-			} // for x
-		} // while
-	} // else no keycheck test
-
-	lcd_tst_next:
-
-	// write a one pixel border around the screen
-	lcd_fg_color = 15;	// VGA Bright White
-	fb_draw_line2(LEFT, TOP, RIGHT, TOP, lcd_fg_color);
-	fb_draw_line2(LEFT, TOP, LEFT, BOTTOM, lcd_fg_color);
-	fb_draw_line2(LEFT, BOTTOM, RIGHT, BOTTOM, lcd_fg_color);	// bottom left to bottom right
-	fb_draw_line2(RIGHT, TOP, RIGHT, BOTTOM, lcd_fg_color);	// bottom right to top right
-	// draw an x
-	fb_draw_line2(LEFT, TOP, RIGHT, BOTTOM, lcd_fg_color);
-	fb_draw_line2(LEFT, BOTTOM, RIGHT, TOP, lcd_fg_color);
-	// draw 3 circles at the center of the screen, one inside the other
-	lcd_fg_color = 12;	// VGA Bright Red
-	fb_draw_circle2(CENTER_X, CENTER_Y, 100, lcd_fg_color);
-	lcd_fg_color = 10;	// VGA Bright Green
-	fb_draw_circle2(CENTER_X, CENTER_Y, 66, lcd_fg_color);
-	lcd_fg_color = 9;	// VGA Bright Blue
-	fb_draw_circle2(CENTER_X, CENTER_Y, 33, lcd_fg_color);
-
-	return 0;
-}
-
-// fb_set_pixel sets a pixel to the specified color.
-// This is target specific and is called from the generic
-// fb_draw.c functions
-void fb_set_pixel(ulong X, ulong Y, uchar color)
-{
-   	// Make sure the specified pixel is valid.
-#if 0
-   	if((X < 0) || (X >= PIXELS_PER_ROW) || (Y < 0) || (Y >= PIXELS_PER_COL))
-   	{   
-		printf("fb_set_pixel() bad X (%ld) or Y (%ld)!\n", X, Y);
-		return;
-   	}
-#else
-	if (X < 0)
-		X = 0;
-	else {
-		if (X >= PIXELS_PER_ROW)
-			X = PIXELS_PER_ROW - 1;
-	}
-	if (Y < 0)
-		Y = 0;
-	else {
-		if (Y >= PIXELS_PER_COL)
-			Y = PIXELS_PER_COL - 1;
-	}
-#endif
-
-	LCD_BUF(LCD_GET_PIXEL_ADD(X, Y)) = vga_lookup[color];
-}
-#endif
diff --git a/ports/beagleboneblack/omap3530_lcd.h b/ports/beagleboneblack/omap3530_lcd.h
deleted file mode 100644
index 0457548..0000000
--- a/ports/beagleboneblack/omap3530_lcd.h
+++ /dev/null
@@ -1,75 +0,0 @@
-//==========================================================================
-//
-// omap3530_lcd.h
-//
-// Author(s):    Luis Torrico, Cogent Computer Systems, Inc.
-// Contributors: 
-// Date:         12/10/2008
-// Description:  This file contains register offsets and bit defines
-//				 for the OMAP3530 Cortex-A8 LCD Controller
-//
-
-#include "bits.h"
-
-/* The DSS is designed to support video and graphics processing functions and to */
-/* interface with video/still image sensors and displays. */
-
-/*-------------------------------------------------------------------------------------*/
-/* Display Interface Subsystem */ 
-/*-------------------------------------------------------------------------------------*/
-/* Module Name				Base Address		Size */
-/* 
-   DSI Protocol Engine		0x4804FC00			512 bytes
-   DSI Complex I/O			0x4804FE00			64 bytes
-   DSI PLL Controller		0x4804FF00			32 bytes
-   DISS						0x48050000			512 byte
-   DISPC					0x48050400			1K byte
-   RFBI						0x48050800			256 bytes
-   VENC						0x48050C00			256 bytes
-*/
-/*-------------------------------------------------------------------------------------*/
-#define DSS_BASE_ADD		0x48050000 		// Display Subsystem Base Address
-#define DISPC_BASE_ADD		0x48050400 		// Display Controller Base Address
-#define DSS_REG(_x_)		*(vulong *)(DSS_BASE_ADD + _x_)
-#define DISPC_REG(_x_)		*(vulong *)(DISPC_BASE_ADD + _x_)
-
-// Display Subsystem Registers
-#define DSS_SYSCONFIG		0x10 		// 
-#define DSS_SYSSTATUS		0x14 		// 
-#define DSS_IRQSTATUS		0x18 		// 
-#define DSS_CONTROL			0x40 		// 
-#define DSS_SDI_CONTROL		0x44 		// 
-#define DSS_PLL_CONTROL		0x48 		// 
-#define DSS_SDI_STATUS		0x5C 		// 
-
-// Display Controller Registers
-#define DISPC_SYSCONFIG			0x10 		// 
-#define DISPC_SYSSTATUS			0x14 		// 
-#define DISPC_IRQSTATUS			0x18 		// 
-#define DISPC_IRQENABLE			0x1C 		// 
-#define DISPC_CONTROL			0x40 		// 
-#define DISPC_CONFIG			0x44 		// 
-#define DISPC_CAPABLE			0x48 		// 
-#define DISPC_DEFAULT_COLOR		0x4C 		// 
-#define DISPC_TRANS_COLOR		0x54 		// 
-#define DISPC_LINE_STATUS		0x5C 		// 
-#define DISPC_LINE_NUMBER		0x60 		// 
-#define DISPC_TIMING_H 			0x64 		// 
-#define DISPC_TIMING_V 			0x68 		// 
-#define DISPC_POL_FREQ			0x6C 		// 
-#define DISPC_DIVISOR			0x70 		// 
-#define DISPC_GLOBAL_ALPHA		0x74 		// 
-#define DISPC_SIZE_DIG			0x78 		// 
-#define DISPC_SIZE_LCD			0x7C 		// 
-#define DISPC_GFX_BA			0x80 		// 
-#define DISPC_GFX_POS			0x88 		// 
-#define DISPC_GFX_SIZE			0x8C 		// 
-#define DISPC_GFX_ATTR			0xA0 		// 
-#define DISPC_GFX_FIFO_TH		0xA4 		// 
-#define DISPC_GFX_FIFO_SS		0xA8 		// 
-#define DISPC_GFX_ROW_INC		0xAC 		// 
-#define DISPC_GFX_PIX_INC		0xB0 		// 
-#define DISPC_GFX_WIN_SKIP		0xB4 		// 
-#define DISPC_GFX_TABLE_BA		0xB8 		// 
-#define DISPC_GFX_PRELOAD		0x62C 		// 
-
diff --git a/ports/beagleboneblack/omap3530_mem.h b/ports/beagleboneblack/omap3530_mem.h
deleted file mode 100644
index 820873c..0000000
--- a/ports/beagleboneblack/omap3530_mem.h
+++ /dev/null
@@ -1,184 +0,0 @@
-//==========================================================================
-//
-// omap3530_mem.h
-//
-// Author(s):    Luis Torrico, Cogent Computer Systems, Inc.
-// Contributors: 
-// Date:         12/09/2008
-// Description:  This file contains register base addresses and offsets
-//				 and access macros for the OMAP3530 Cortex-A8 memory controller
-//
-
-#include "bits.h"
-
-// The GPMC supports up to eight chip-select regions of programmable size, and programmable base
-// addresses in a total address space of 1 Gbyte. 
-// Chip Select mapping for CSB740 
-// CS0 = NOR = 0x08000000 
-// CS1 = N/A 
-// CS2 = N/A 
-// CS3 = NAND = 0x18000000 
-// CS4 = Ethernet = 0x2C000000 
-// CS5 = Expansion = 0x28000000 
-// CS6 = N/A  
-// CS7 = N/A  
-
-//#define OMAP35XX_GPMC_BASE	0x6E000000
-#define GPMC_REG(_x_)		*(vulong *)(OMAP35XX_GPMC_BASE + _x_)
-#define MYGPMC_REG(_x_)		(vulong *)(OMAP35XX_GPMC_BASE + _x_)
-
-// GPMC - General Purpose Memory Controller
-#define GPMC_SYS_CONFIG		0x10 	// Chip Select 0 Upper Control Register
-#define GPMC_SYS_STATUS		0x14 	// Chip Select 0 Lower Control Register
-#define GPMC_IRQ_STATUS		0x18 	// Chip Select 0 Additional Control Register
-#define GPMC_IRQ_EN			0x1C 	// Chip Select 1 Upper Control Register
-#define GPMC_TIMEOUT		0x40 	// Chip Select 1 Lower Control Register
-#define GPMC_ERR_ADD		0x44 	// Chip Select 1 Additional Control Register
-#define GPMC_ERR_TYPE		0x48 	// Chip Select 2 Upper Control Register
-#define GPMC_CONFIG			0x50 	// Chip Select 2 Lower Control Register
-#define GPMC_STATUS			0x54 	// Chip Select 2 Additional Control Register
-
-#define GPMC_CS0_CONFIG1	0x60 	// Chip Select 3 Upper Control Register
-#define GPMC_CS0_CONFIG2	0x64 	// Chip Select 3 Lower Control Register
-#define GPMC_CS0_CONFIG3	0x68 	// Chip Select 3 Additional Control Register
-#define GPMC_CS0_CONFIG4	0x6C 	// Chip Select 4 Upper Control Register
-#define GPMC_CS0_CONFIG5	0x70 	// Chip Select 4 Lower Control Register
-#define GPMC_CS0_CONFIG6	0x74 	// Chip Select 4 Additional Control Register
-#define GPMC_CS0_CONFIG7	0x78 	// Chip Select 5 Upper Control Register
-
-#define GPMC_CS1_CONFIG1	0x90 	// Chip Select 5 Lower Control Register
-#define GPMC_CS1_CONFIG2	0x94 	// Chip Select 5 Additional Control Register
-#define GPMC_CS1_CONFIG3	0x98 	// Configuration Register
-#define GPMC_CS1_CONFIG4	0x9C 	// Chip Select 5 Lower Control Register
-#define GPMC_CS1_CONFIG5	0xA0 	// Chip Select 5 Additional Control Register
-#define GPMC_CS1_CONFIG6	0xA4 	// Configuration Register
-#define GPMC_CS1_CONFIG7	0xA8 	// Configuration Register
-
-#define GPMC_CS2_CONFIG1	0xC0 	// Chip Select 5 Lower Control Register
-#define GPMC_CS2_CONFIG2	0xC4 	// Chip Select 5 Additional Control Register
-#define GPMC_CS2_CONFIG3	0xC8 	// Configuration Register
-#define GPMC_CS2_CONFIG4	0xCC 	// Chip Select 5 Lower Control Register
-#define GPMC_CS2_CONFIG5	0xD0 	// Chip Select 5 Additional Control Register
-#define GPMC_CS2_CONFIG6	0xD4 	// Configuration Register
-#define GPMC_CS2_CONFIG7	0xD8 	// Configuration Register
-
-#define GPMC_CS3_CONFIG1	0xF0 	// Chip Select 5 Lower Control Register
-#define GPMC_CS3_CONFIG2	0xF4 	// Chip Select 5 Additional Control Register
-#define GPMC_CS3_CONFIG3	0xF8 	// Configuration Register
-#define GPMC_CS3_CONFIG4	0xFC 	// Chip Select 5 Lower Control Register
-#define GPMC_CS3_CONFIG5	0x100 	// Chip Select 5 Additional Control Register
-#define GPMC_CS3_CONFIG6	0x104 	// Configuration Register
-#define GPMC_CS3_CONFIG7	0x108 	// Configuration Register
-
-#define GPMC_CS4_CONFIG1	0x120 	// Chip Select 5 Lower Control Register
-#define GPMC_CS4_CONFIG2	0x124 	// Chip Select 5 Additional Control Register
-#define GPMC_CS4_CONFIG3	0x128 	// Configuration Register
-#define GPMC_CS4_CONFIG4	0x12C 	// Chip Select 5 Lower Control Register
-#define GPMC_CS4_CONFIG5	0x130 	// Chip Select 5 Additional Control Register
-#define GPMC_CS4_CONFIG6	0x134 	// Configuration Register
-#define GPMC_CS4_CONFIG7	0x138 	// Configuration Register
-
-#define GPMC_CS5_CONFIG1	0x150 	// Chip Select 5 Lower Control Register
-#define GPMC_CS5_CONFIG2	0x154 	// Chip Select 5 Additional Control Register
-#define GPMC_CS5_CONFIG3	0x158 	// Configuration Register
-#define GPMC_CS5_CONFIG4	0x15C 	// Chip Select 5 Lower Control Register
-#define GPMC_CS5_CONFIG5	0x160 	// Chip Select 5 Additional Control Register
-#define GPMC_CS5_CONFIG6	0x164 	// Configuration Register
-#define GPMC_CS5_CONFIG7	0x168 	// Configuration Register
-
-#define GPMC_CS6_CONFIG1	0x180 	// Chip Select 5 Lower Control Register
-#define GPMC_CS6_CONFIG2	0x184 	// Chip Select 5 Additional Control Register
-#define GPMC_CS6_CONFIG3	0x188 	// Configuration Register
-#define GPMC_CS6_CONFIG4	0x18C 	// Chip Select 5 Lower Control Register
-#define GPMC_CS6_CONFIG5	0x190 	// Chip Select 5 Additional Control Register
-#define GPMC_CS6_CONFIG6	0x194 	// Configuration Register
-#define GPMC_CS6_CONFIG7	0x198 	// Configuration Register
-
-#define GPMC_CS7_CONFIG1	0x1B0 	// Chip Select 5 Lower Control Register
-#define GPMC_CS7_CONFIG2	0x1B4 	// Chip Select 5 Additional Control Register
-#define GPMC_CS7_CONFIG3	0x1B8 	// Configuration Register
-#define GPMC_CS7_CONFIG4	0x1BC 	// Chip Select 5 Lower Control Register
-#define GPMC_CS7_CONFIG5	0x1C0 	// Chip Select 5 Additional Control Register
-#define GPMC_CS7_CONFIG6	0x1C4 	// Configuration Register
-#define GPMC_CS7_CONFIG7	0x1C8 	// Configuration Register
-
-#define GPMC_PREFETCH_CONFIG1	0x1E0 	
-#define GPMC_PREFETCH_CONFIG2	0x1E4 	
-#define GPMC_PREFETCH_CONTROL	0x1EC 	
-#define GPMC_PREFETCH_STATUS	0x1F0 	
-
-// Bit Defines for OMAP3530 GPMC
-// WEIM_CS0U to WEIM_CS5U - Chip Select Upper Control Register
-#define WEIM_CSU_SP				BIT31					// Supervisor Protect, 0 = User mode accesses allowed, 1 = User mode accesses prohibited
-#define WEIM_CSU_WP				BIT30					// Write Protect, 0 = Writes allowed, 1 = Writes prohibited
-#define WEIM_CSU_BCD(_x_)		((_x_ & 0x03) << 28)	// Burst Clock Divisor, when EIM_CFG_BCM = 0
-#define WEIM_CSU_BCS(_x_)		((_x_ & 0x03) << 24)	// Burst Clock Start, # of 1/2 cycles from LBA to BCLK high
-#define WEIM_CSU_PSZ_4			(0 << 22)				// page size = 4 words
-#define WEIM_CSU_PSZ_8			(1 << 22)				// page size = 8 words
-#define WEIM_CSU_PSZ_16			(2 << 22)				// page size = 16 words
-#define WEIM_CSU_PSZ_32			(3 << 22)				// page size = 32 words
-#define WEIM_CSU_PME			BIT21					// 1 = Enables page mode emulation
-#define WEIM_CSU_SYNC			BIT20					// 1 = Enables synchronous burst mode
-#define WEIM_CSU_DOL(_x_)		((_x_ & 0x0f) << 16)	// # of clocks -1 before latching read data when SYNC = 1		
-#define WEIM_CSU_CNC_0			(0 << 14)				// Hold CS negated after end of cycle for 0 clocks
-#define WEIM_CSU_CNC_1			(1 << 14)				// Hold CS negated after end of cycle for 1 clock
-#define WEIM_CSU_CNC_2			(2 << 14)				// Hold CS negated after end of cycle for 2 clocks
-#define WEIM_CSU_CNC_3			(3 << 14)				// Hold CS negated after end of cycle for 3 clocks
-#define WEIM_CSU_WSC(_x_)		((_x_ & 0x3f) << 8)		// Wait States, 0 = 2, 1 = 2, 2-62 = +1, 63 = dtack
-#define WEIM_CSU_WSC_DTACK		(0x3f << 8)		        // Wait States, 0 = 2, 1 = 2, 2-62 = +1, 63 = dtack
-#define WEIM_CSU_EW				BIT7					// Determines how WEIM supports the ECB input
-#define WEIM_CSU_WWS(_x_)		((_x_ & 0x07) << 4)		// Additional wait states for write cycles
-#define WEIM_CSU_EDC(_x_)		((_x_ & 0x0f) << 0)		// Dead Cycles after reads for bus turn around
-
-// Bit Defines for MCIMX31
-// WEIM_CS0L to WEIM_CS5L - Chip Select Lower Control Register
-#define WEIM_CSL_OEA(_x_)		((_x_ & 0x0f) << 28)	// # of 1/2 cycles after CS asserts before OE asserts
-#define WEIM_CSL_OEN(_x_)		((_x_ & 0x0f) << 24)	// # of 1/2 cycles OE negates before CS negates
-#define WEIM_CSL_WEA(_x_)		((_x_ & 0x0f) << 20)	// # of 1/2 cycles EB0-3 assert before WE asserts
-#define WEIM_CSL_WEN(_x_)		((_x_ & 0x0f) << 16)	// # of 1/2 cycles EB0-3 negate before WE negates 
-#define WEIM_CSL_CSA(_x_)		((_x_ & 0x0f) << 12)	// # of clocks address is asserted before CS and held after CS
-#define WEIM_CSL_EBC			BIT11					// 0 = assert EB0-3 for Reads & Writes, 1 = Writes only
-#define WEIM_CSL_DSZ_BYTE_3		(0 << 8)				// device is 8-bits wide, located on byte 3 (D31-24)
-#define WEIM_CSL_DSZ_BYTE_2		(1 << 8)				// device is 8-bits wide, located on byte 2 (D23-16)
-#define WEIM_CSL_DSZ_BYTE_1		(2 << 8)				// device is 8-bits wide, located on byte 1 (D15-8)
-#define WEIM_CSL_DSZ_BYTE_0		(3 << 8)				// device is 8-bits wide, located on byte 0 (D7-0)
-#define WEIM_CSL_DSZ_HALF_1		(4 << 8)				// device is 16-bits wide, located on half word 1 (D31-16)
-#define WEIM_CSL_DSZ_HALF_0		(5 << 8)				// device is 16-bits wide, located on half word 1 (D15-0)
-#define WEIM_CSL_DSZ_WORD		(6 << 8)				// device is 32-bits wide, located on half word 1 (D15-0)
-#define WEIM_CSL_CSN(_x_)		((_x_ & 0x0f) << 4)	  	// Chip Select Negate
-#define WEIM_CSL_PSR			BIT3					// PSRAM Enable, 0 = disabled, 1 = enabled
-#define WEIM_CSL_CRE			BIT2					// Control Register Enable
-#define WEIM_CSL_WRAP			BIT1					// 0 = Memory in linear mode, 1 = Memory in wrap mode
-#define WEIM_CSL_CSEN			BIT0					// 1 = Enable Chip Select
-
-// Bit Defines for MCIMX31
-// WEIM_CS0A to WEIM_CS5A - Chip Select Additional Control Register
-#define WEIM_CSA_EBRA(_x_)		((_x_ & 0x0f) << 28)	// # of half AHB clock cycles before EB asserted.
-#define WEIM_CSA_EBRN(_x_)		((_x_ & 0x0f) << 24)	// # of half AHB clock cycles between EB negation and end of access.
-#define WEIM_CSA_RWA(_x_)		((_x_ & 0x0f) << 20)	// # of half AHB clock cycles RW delay
-#define WEIM_CSA_RWN(_x_)		((_x_ & 0x0f) << 16)	// # of half AHB clock cycles between EB negation and end of access
-#define WEIM_CSA_MUM			BIT15					// 1 = Muxed Mode
-#define WEIM_CSA_LAH_0			(0 << 13)				// 0 AHB half clock cycles between LBA negation and address invalid
-#define WEIM_CSA_LAH_1			(1 << 13)				// 1 AHB half clock cycles between LBA negation and address invalid
-#define WEIM_CSA_LAH_2			(2 << 13)				// 2 AHB half clock cycles between LBA negation and address invalid
-#define WEIM_CSA_LAH_3			(3 << 13)				// 3 AHB half clock cycles between LBA negation and address invalid
-#define WEIM_CSA_LBN(_x_)		((_x_ & 0x07) << 10)		// This bit field determines when LBA is negated
-#define WEIM_CSA_LBA_0			(0 << 8)				// 0 AHB half clock cycles between beginning of access and LBA assertion.
-#define WEIM_CSA_LBA_1			(1 << 8)				// 1 AHB half clock cycles between beginning of access and LBA assertion.
-#define WEIM_CSA_LBA_2			(2 << 8)				// 2 AHB half clock cycles between beginning of access and LBA assertion.
-#define WEIM_CSA_LBA_3			(3 << 8)				// 3 AHB half clock cycles between beginning of access and LBA assertion.
-#define WEIM_CSA_DWW(_x_)		((_x_ & 0x03) << 6)	  	// Decrease Write Wait State
-#define WEIM_CSA_DCT_0			(0 << 4)				// 0 AHB clock cycles between CS assertion and first DTACK check.
-#define WEIM_CSA_DCT_1			(1 << 4)				// 1 AHB clock cycles between CS assertion and first DTACK check.
-#define WEIM_CSA_DCT_2			(2 << 4)				// 2 AHB clock cycles between CS assertion and first DTACK check.
-#define WEIM_CSA_DCT_3			(3 << 4)				// 3 AHB clock cycles between CS assertion and first DTACK check.
-#define WEIM_CSA_WWU			BIT3					// 1 = Allow wrap on write
-#define WEIM_CSA_AGE			BIT2					// 1 = Enable glue logic
-#define WEIM_CSA_CNC2			BIT1					// Chip Select Negation Clock Cycles
-#define WEIM_CSA_FCE			BIT0					// 1 = Data captured using BCLK_FB
-
-// WEIM_CFG - Configuration Register
-#define WEIM_CFG_BCM			BIT2					// 1 = Burst Clock always on, 0 = when CS with SYNC = 1 is accessed
-#define WEIM_CFG_MAS			BIT0					// 1 = Merged address space
-
-
diff --git a/ports/beagleboneblack/omap3530_sdmmc.c b/ports/beagleboneblack/omap3530_sdmmc.c
deleted file mode 100644
index b542d4e..0000000
--- a/ports/beagleboneblack/omap3530_sdmmc.c
+++ /dev/null
@@ -1,505 +0,0 @@
-/* NOTE:
- * THIS CODE IS NOT READY FOR USE YET!!!
- */
-#include "config.h"
-#include "cpuio.h"
-#include "genlib.h"
-#include "stddefs.h"
-#include "timer.h"
-#include "omap3530.h"
-#include "sd.h"
-
-
-#define MMCTMOUT	2000
-
-/* This code is included here just for simulating the SD
- * interface (temporarily if a real one isn't ready.  In a real system,
- * the INCLUDE_SD_DUMMY_FUNCS definition would be off.
- */
-int
-xsdCmd(unsigned long cmd, unsigned short argh, unsigned short argl)
-{
-	vulong	stat, rsp;
-	struct elapsed_tmr tmr;
-
-	printf("sdCmd(0x%08lx) (cmd=%d)\n",cmd,(cmd & 0x3f000000) >> 24);
-
- 	startElapsedTimer(&tmr,MMCTMOUT);		// Wait for command line not-in-use
-	while(MMC1_REG(MMCHS_PSTATE) & CMDI) {
-		if(msecElapsed(&tmr)) {
-            printf("sdInit: CMDI timeout\n");
-            return(-1);
-        }
-	}
-
-	MMC1_REG(MMCHS_ARG) = ((argh << 16) | argl);
-	MMC1_REG(MMCHS_IE) = 0xfffffeff;
-	MMC1_REG(MMCHS_CMD) = cmd;
-
-again:
-	stat = MMC1_REG(MMCHS_STAT);
-	if (stat & CTO) {
-		if (stat & CCRC)
-			printf("cmdline in use\n");
-		else
-			printf("CTO1 CCRC0\n");
-		MMC1_REG(MMCHS_SYSCTL) |= SRC;
-		startElapsedTimer(&tmr,MMCTMOUT);	
-		while(MMC1_REG(MMCHS_SYSCTL) & SRC) {
-			if(msecElapsed(&tmr))
-				printf("sdInit: SRC timeout\n");
-		}
-		return(-1);
-	}
-	if ((stat & CC)  == 0)
-		goto again;
-		
-	cmd = MMC1_REG(MMCHS_CMD);
-	if ((cmd & RSPTYPE) == RSPTYPE_NONE) {
-		printf("Success!\n");	
-		return(0);
-	}
-
-	if ((cmd & RSPTYPE) == RSPTYPE_136) {
-		rsp = MMC1_REG(MMCHS_RSP10);
-		printf("RSP0: %04x, RSP1: %04x\n",
-			rsp & 0xffff,(rsp & 0xffff0000) >> 16);
-		rsp = MMC1_REG(MMCHS_RSP32);
-		printf("RSP2: %04x, RSP3: %04x\n",
-			rsp & 0xffff,(rsp & 0xffff0000) >> 16);
-		rsp = MMC1_REG(MMCHS_RSP54);
-		printf("RSP4: %04x, RSP5: %04x\n",
-			rsp & 0xffff,(rsp & 0xffff0000) >> 16);
-		rsp = MMC1_REG(MMCHS_RSP76);
-		printf("RSP6: %04x, RSP7: %04x\n",
-			rsp & 0xffff,(rsp & 0xffff0000) >> 16);
-	}
-	if ((cmd & RSPTYPE) == RSPTYPE_48) {
-		rsp = MMC1_REG(MMCHS_RSP10);
-		printf("RSP0: %04x, RSP1: %04x\n",
-			rsp & 0xffff,(rsp & 0xffff0000) >> 16);
-		rsp = MMC1_REG(MMCHS_RSP32);
-		printf("RSP2: %04x, RSP3: %04x\n",
-			rsp & 0xffff,(rsp & 0xffff0000) >> 16);
-	}
-	if ((cmd & RSPTYPE) == RSPTYPE_48BSY) {
-		rsp = MMC1_REG(MMCHS_RSP10);
-		printf("RSP0: %04x, RSP1: %04x\n",
-			rsp & 0xffff,(rsp & 0xffff0000) >> 16);
-		rsp = MMC1_REG(MMCHS_RSP32);
-		printf("RSP2: %04x, RSP3: %04x\n",
-			rsp & 0xffff,(rsp & 0xffff0000) >> 16);
-	}
-
-	return(0);
-}
-
-int
-sdCmd(unsigned long cmd, unsigned short argh, unsigned short argl)
-{
-	vulong	stat, arg;
-	struct elapsed_tmr tmr;
-
-	printf("sdCmd(0x%08lx) (cmd=%d)\n",cmd,(cmd & 0x3f000000) >> 24);
-
-	MMC1_REG(MMCHS_STAT) = 0xffffffff;
-	MMC1_REG(MMCHS_BLK) =  NBLK(1) | BLEN(512);
-	MMC1_REG(MMCHS_SYSCTL) &=  ~DTOMSK;
-	MMC1_REG(MMCHS_SYSCTL) |= DTO(14);
-
- 	startElapsedTimer(&tmr,MMCTMOUT);		// Wait for command line not-in-use
-	while(MMC1_REG(MMCHS_PSTATE) & CMDI) {
-		if(msecElapsed(&tmr)) {
-            printf("sdCmd: CMDI timeout\n");
-            return(-1);
-        }
-		monDelay(1);
-	}
-
-	arg = argh;
-	arg <<= 16;
-	arg |= argl;
-	MMC1_REG(MMCHS_ARG) = arg;
-	MMC1_REG(MMCHS_IE) = 0xfffffeff;
-	MMC1_REG(MMCHS_CMD) = cmd;
-
- 	startElapsedTimer(&tmr,MMCTMOUT);
-	do {
-		stat = MMC1_REG(MMCHS_STAT);
-		if (stat & CTO) {
-			if (stat & CCRC)
-				printf("CCRC1\n");
-			else
-				printf("CTO1 CCRC0\n");
-			MMC1_REG(MMCHS_SYSCTL) |= SRC;
-			startElapsedTimer(&tmr,MMCTMOUT);	
-			while(MMC1_REG(MMCHS_SYSCTL) & SRC) {
-				if(msecElapsed(&tmr))
-					printf("sdCmd: SRC timeout\n");
-			}
-			return(-1);
-		}
-		if(msecElapsed(&tmr)) {
-            printf("sdCmd: CC timeout\n");
-            return(-1);
-        }
-		monDelay(1);
-	} while ((stat & CC) == 0);
-
-	stat = MMC1_REG(MMCHS_STAT);
-	if (stat & CCRC) 
-		printf("Cmd crc\n");
-	if (stat & DCRC) 
-		printf("Data crc\n");
-	if (stat & CERR)  {
-		printf("Card error 0x%lx\n",stat);
-		return(-1);
-	}
-	if (stat & CTO) {
-		printf("CTO set!\n");
-		return(-1);
-	}
-	if (stat & CC) {
-		printf("Success!\n");	
-		return(0);
-	}
-	else {
-		printf("Didn't complete!\n");	
-		return(-1);
-	}
-}
-
-int
-sdClkSet(int clkval)
-{
-	vulong reg;
-	struct elapsed_tmr tmr;
-
-	MMC1_REG(MMCHS_SYSCTL) &= ~CEN;
-	reg = MMC1_REG(MMCHS_SYSCTL);
-	reg &= ~CLKDMSK;
-	reg |= CLKD(96000/clkval);
-	MMC1_REG(MMCHS_SYSCTL) = reg;
-
- 	startElapsedTimer(&tmr,MMCTMOUT);			// Wait for clock stable
-	while((MMC1_REG(MMCHS_SYSCTL) & ICS) == 0) {
-		if(msecElapsed(&tmr)) {
-			printf("sdClkSet: ICS timeout\n");
-			return(-1);
-		}
-		monDelay(1);
-	}
-	MMC1_REG(MMCHS_SYSCTL) |= CEN;
-	startElapsedTimer(&tmr,MMCTMOUT);			// Wait for clock stable
-	while((MMC1_REG(MMCHS_SYSCTL) & CEN) == 0) {
-		if(msecElapsed(&tmr)) {
-            printf("sdClkSet: ICS timeout\n");
-            return(-1);
-        }
-		monDelay(1);
-	}
-	return(0);
-}
-
-/* sdInit():
- * This function is called by the "sd init" command on the command line.
- * Where applicable, the text refers to the section in the Sept 2008 
- * Technical Reference Manual (TRM) from which I got the code/functionality.
- */
-int
-sdInit(int interface, int verbose)
-{
-	int i, pbiasretry = 0;
-	vulong reg;
-	struct elapsed_tmr tmr;
-
-	/* There's only one interface on the CSB740, so reject anything
-	 * other than interface 0...
-	 */
-	if (interface != 0)
-		return(-1);
-
-	/*******************************
-	 *
-	 * Clock configuration:
-	 * (TRM 22.5.1.1)
-	 */
-	*(vulong *)CM_ICLKEN1_CORE |= EN_MMC1;	// Configure interface and
-	*(vulong *)CM_FCLKEN1_CORE |= EN_MMC1;	// functional clocks.
-
-	/*******************************
-	 *
-	 * Not really sure what this is... apparently some kind of clock steering.
-	 * I tried both setting the bit and clearing it.  Made no difference.
-	 * In both cases the clock was present on the CLK pin.
-	 */
-	*(vulong *)CONTROL_DEVCONF0 |= MMCSDIO1ADPCLKISEL;
-
-	/********************************
-	 *
-	 * Set up BIAS (this allows the pins to run at 1.8 or 3.0 volts I think).
-	 * This is configured as 0606 in rom_reset.S (i don't think thats right).
-	 * Note: The CSB703 ties this interface to 3.3 volts.
-	 * TRM 22.5.3
-	 * TRM 7.5.2 and flowchart in figure 7-24...
-	 */
-pbias_retry:
-	*(vulong *)CONTROL_PBIAS_LITE = PBIAS_LITE_VMMC1_52MHZ;
-	monDelay(100);
-	*(vulong *)CONTROL_PBIAS_LITE |= MMC_PWR_STABLE;
-	monDelay(100);
-	if (*(vulong *)CONTROL_PBIAS_LITE & PBIAS_LITE_MMC1_ERROR) {
-		*(vulong *)CONTROL_PBIAS_LITE &= (~MMC_PWR_STABLE);
-		monDelay(100);
-		if (pbiasretry++ < 3) {
-			goto pbias_retry;
-		}
-		else {
-            printf("sdInit: PBIAS timeout\n");
-            return(-1);
-		}
-	}
-
-#if 0
-	/*******************************
-	 *
-	 * These registers are things I found when scouring the TRM for "MMC".
-	 * I don't think they have any affect on basic startup of the interface
-	 * so they are removed for now...
-	 */
-	*(vulong *)CM_AUTOIDLE1_CORE &= ~AUTO_MMC1;		// Disable auto clock enable
-	*(vulong *)PM_WKEN1_CORE &= ~EN_MMC1;			// Disable wakeup event
-	*(vulong *)PM_MPUGRPSEL1_CORE &= ~GRPSEL_MMC1;	// Disable mpu-group wakeup
-	*(vulong *)PM_IVA2GRPSEL1_CORE &= ~GRPSEL_MMC1;	// Disable iva2-group wakeup
-	*(vulong *)PM_WKST1_CORE &= ~EN_MMC1;			// Clear wakeup status
-#endif
-
-	/*******************************
-	 *
-	 * Issue soft reset and wait for completion...
-	 * (TRM 22.5.1.2)
-	 */
-	MMC1_REG(MMCHS_SYSCONFIG) |= SRESET;			// Software reset
-	if ((MMC1_REG(MMCHS_SYSSTATUS) & RESETDONE) == 0)
-		printf("Good, RESETDONE is low here\n");
-
- 	startElapsedTimer(&tmr,MMCTMOUT);					// Wait for completion
-	while((MMC1_REG(MMCHS_SYSSTATUS) & RESETDONE) == 0) {
-		if(msecElapsed(&tmr)) {
-            printf("sdInit: SRST failed\n");
-            return(-1);
-        }
-	}
-	/********************************
-	 *
-	 * Set SRA bit, then wait for it to clear.
-	 */
-	MMC1_REG(MMCHS_SYSCTL) |= SRA;
- 	startElapsedTimer(&tmr,MMCTMOUT);
-	while((MMC1_REG(MMCHS_SYSCTL) & SRA)) {
-		if(msecElapsed(&tmr)) {
-            printf("sdInit: SRA timeout\n");
-            return(-1);
-        }
-	}
-	
- 	startElapsedTimer(&tmr,MMCTMOUT);		// Wait for debounce stable.
-	while((MMC1_REG(MMCHS_PSTATE) & DEBOUNCE) != DEBOUNCE) {
-		if(msecElapsed(&tmr)) {
-            printf("sdInit: DEBOUNCE timeout\n");
-            return(-1);
-        }
-	}
-
-	/*******************************
-	 *
-	 * Establish hardware capabilities:
-	 * TRM 22.5.1.3
-	 */
-	reg = MMC1_REG(MMCHS_CAPA);
-	reg &= ~(VS18 | VS30 | VS33);
-	reg |= VS18;
-	MMC1_REG(MMCHS_CAPA) = reg;
-
-#if 0
-	/********************************
-	 *
-	 * Enable wakeup mode (don't think I need this, tried both ways)
-	 * TRM 22.5.1.4
-	 */
-	MMC1_REG(MMCHS_SYSCONFIG) |= ENWAKEUP;
-	MMC1_REG(MMCHS_HCTL) |= IWE;
-#endif
-	
-	/********************************
-	 *
-	 * MMC Host and Bus Configuration
-	 * TRM 22.5.1.5
-	 */
-	//MMC1_REG(MMCHS_CON) =
-	MMC1_REG(MMCHS_HCTL) &= ~SVDS;
-	MMC1_REG(MMCHS_HCTL) |= SVDS18;
-	monDelay(10);
-	MMC1_REG(MMCHS_HCTL) |= SDBP;
-	monDelay(100);
-	
- 	startElapsedTimer(&tmr,MMCTMOUT);			// Wait for SVDS verification
-	while((MMC1_REG(MMCHS_HCTL) & SDBP) == 0) {
-		if(msecElapsed(&tmr)) {
-            printf("sdInit: SDBP timeout\n");
-            return(-1);
-        }
-	}
-
-	MMC1_REG(MMCHS_SYSCTL) |= ICE;			// Enable internal clock
-
-	MMC1_REG(MMCHS_SYSCTL) &= ~CLKDMSK;		// Set clock divisor:
-	MMC1_REG(MMCHS_SYSCTL) |= CLKD(960);	// (should be <= 80Khz initially)
-
- 	startElapsedTimer(&tmr,MMCTMOUT);			// Wait for clock stable
-	while((MMC1_REG(MMCHS_SYSCTL) & ICS) == 0) {
-		if(msecElapsed(&tmr)) {
-            printf("sdInit: ICS timeout\n");
-            return(-1);
-        }
-	}
-
-	/* I set these two bits with the hope that the clock will be
-	 * active even if there is no card installed (so I atleast can
-	 * see *some* activity).
-	 */
-	MMC1_REG(MMCHS_SYSCTL) |= CEN;			// External clock enable
-#if 0
-	MMC1_REG(MMCHS_CON) |= CLKEXTFREE;
-
-	reg = MMC1_REG(MMCHS_SYSCONFIG);
-	reg &= ~SIDLEMODEMSK;
-	reg &= ~CLKACTIVITYMSK;
-	reg &= ~AUTOIDLE;
-	reg |= (SIDLEMODE(1) | CLKACTIVITY(3));
-	MMC1_REG(MMCHS_SYSCONFIG) = reg;
-#endif
-
-	/********************************
-	 *
-	 * Set the INIT bit to send an initialization stream to the card...
-	 * (top of left flowchart in TRM section 22.5.2.1)
-	 */
-	MMC1_REG(MMCHS_CON) |= MMCINIT;
-	for(i=0;i<10;i++) {
-		sdCmd(CMD(0) | RSPTYPE_NONE,0,0);
-		monDelay(2);
-	}
-	MMC1_REG(MMCHS_CON) &= ~MMCINIT;
-	MMC1_REG(MMCHS_STAT) = 0xffffffff;
-
-	if (sdClkSet(400) != 0)
-		return(-1);
-
-	/* this is the get_card_type() function in the code from TI...
-	 */
-	if (sdCmd(CMD(55) | RSPTYPE_48,0,0) < 0) {
-		printf("Card type = MMC\n");
-		MMC1_REG(MMCHS_CON) |= ODE;
-	}
-	else {
-		if ((MMC1_REG(MMCHS_RSP10) & 0xffff) == 0x0120) {
-			printf("Card type = SD\n");
-		}
-		else {
-			printf("Card type = MMC_CARD\n");
-			MMC1_REG(MMCHS_CON) |= ODE;
-		}
-	}
-
-	
-#if 0
-	/********************************
-	 *
-	 * Send Command 5
-	 * (top of right flowchart in TRM section 22.5.2.1)
-	 */
-	sdCmd(CMD(5) | RSPTYPE_NONE,0,0);
-
- 	startElapsedTimer(&tmr,MMCTMOUT);
-	do {
-		reg = MMC1_REG(MMCHS_STAT);
-		if (reg & CC) {
-			/* For now we assume only SD cards... */
-			printf("SDIO detected!!!  Shouldn't be here!\n");
-			return(-1);
-		}
-		if(msecElapsed(&tmr)) {
-            printf("sdInit: CTO timeout1\n");
-            return(-1);
-        }
-		
-	} while((reg & CTO) == 0);
-
-	/********************************
-	 *
-	 * Set SRC bit, then wait for it to clear.
-	 * (midway down right flowchart in TRM section 22.5.2.1)
-	 */
-	MMC1_REG(MMCHS_SYSCTL) |= SRC;
- 	startElapsedTimer(&tmr,MMCTMOUT);
-	while((MMC1_REG(MMCHS_SYSCTL) & SRC)) {
-		if(msecElapsed(&tmr)) {
-            printf("sdInit: SRC timeout\n");
-            return(-1);
-        }
-	}
-
-	sdCmd(CMD(8) | RSPTYPE_NONE,0,0);
-
- 	startElapsedTimer(&tmr,MMCTMOUT);
-	do {
-		reg = MMC1_REG(MMCHS_STAT);
-		if (reg & CC) {
-			/* For now we assume only SD cards... */
-			printf("SD BINGO!!!  This is where we want to be!\n");
-			return(0);
-		}
-		if(msecElapsed(&tmr)) {
-            printf("sdInit: CTO timeout2\n");
-            return(-1);
-        }
-		
-	} while((reg & CTO) == 0);
-
-	/* For now we assume only SD cards... */
-	printf("MMC detected!!!  Shouldn't be here!\n");
-#endif
-	return(-1);
-}
-
-int
-sdRead(int interface, char *buf, int blk, int blkcnt)
-{
-	char *from;
-	int	size;
-
-	if (interface != 0)
-		return(-1);
-
-	from = (char *)(blk * SD_BLKSIZE);
-	size = blkcnt * SD_BLKSIZE;
-	memcpy(buf,from,size);
-	return(0);
-}
-
-int
-sdWrite(int interface, char *buf, int blk, int blkcnt)
-{
-	char *to;
-	int	size;
-
-	if (interface != 0)
-		return(-1);
-
-	to = (char *)(blk * SD_BLKSIZE);
-	size = blkcnt * SD_BLKSIZE;
-	memcpy(to,buf,size);
-	return(0);
-}
-
-- 
2.3.3




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