[PATCH 03/13] Replaced cpuio.c and cpuio.h in BBB port
Gedare Bloom
gedare at gwu.edu
Mon Jun 22 13:23:41 UTC 2015
Add your own header to files where you delete the existing one. Strive
for consistency :)
On Fri, Jun 19, 2015 at 10:57 PM, Jarielle Catbagan
<jcatbagan93 at gmail.com> wrote:
> The former cpuio.* files contained code specific to CSB740. It was replaced with
> the template cpuio.* files with the getUartDivisor() function retained from the
> previous cpuio.c
> ---
> ports/beagleboneblack/cpuio.c | 348 ++++++++++--------------------------------
> ports/beagleboneblack/cpuio.h | 77 +---------
> 2 files changed, 79 insertions(+), 346 deletions(-)
>
> diff --git a/ports/beagleboneblack/cpuio.c b/ports/beagleboneblack/cpuio.c
> index 0a9a262..8f2fbed 100644
> --- a/ports/beagleboneblack/cpuio.c
> +++ b/ports/beagleboneblack/cpuio.c
> @@ -1,64 +1,11 @@
> -//=============================================================================
> -//
> -// cpuio.c
> -//
> -// CPU/Board Specific IO
> -//
> -// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
> -// Date: 12/04/2008
> -// Description: This file contains the IO functions required by Micro Monitor
> -// that are unique to the CSB740
> -//
> -//
> -//=============================================================================
> -
> #include "config.h"
> +#include "stddefs.h"
> #include "cpuio.h"
> #include "genlib.h"
> -#include "ether.h"
> -#include "stddefs.h"
> +#include "cache.h"
> #include "warmstart.h"
> -#include "omap3530.h"
> -#include "omap3530_mem.h"
> -#include "cpu_gpio.h"
> -#include "fb_draw.h"
> -#include "uart16550.h"
> -#include "umongpio.h"
> -#include "ad7843.h"
> -
> -#define __raw_readl(a) (*(volatile unsigned int *)(a))
> -
> -extern ulong i2c_init(void);
> -extern ulong getpsr(void);
> -extern void putpsr(ulong);
> -
> -uchar bcolor=0; // vga black
> -
> -/******************************************************
> -// Delay for some usecs. - Not accurate, assumes ROM mode
> -// and no Cache
> - ******************************************************/
> -void udelay(int delay)
> -{
> - volatile int i;
> - for ( i = LOOPS_PER_USEC * delay; i ; i--);
> -}
> +#include "timer.h"
>
> -/******************************************************
> - * Routine: wait_for_command_complete
> - * Description: Wait for posting to finish on watchdog
> - ******************************************************/
> -void wait_for_command_complete(unsigned int wd_base)
> -{
> - int pending = 1;
> - do {
> - pending = __raw_readl(wd_base + WD_WWPS);
> - } while (pending);
> -}
> -
> -/******************************************************
> -// getUARTDivisor is called from UART16550.c
> - ******************************************************/
> int
> getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
> {
> @@ -67,247 +14,106 @@ getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
> return(0);
> }
>
> -/******************************************************
> -// Set pads (pins) to correct mode. Refer to section 7.4.4
> - in TI omap35xx_tech_ref_manual for bit defines.
> - ******************************************************/
> -void pads_init()
> -{
> - // Set up chip selects
> - SCM_REG(PADCONFS_GPMC_NCS3) = 0x00180018; // NCS3[15:0], NCS4[31:16]
> - SCM_REG(PADCONFS_GPMC_NCS5) = 0x011C0018; // NCS5[15:0], EXP_INTX[31:16]
> -
> - // Set LCD_BKL_X to output, pullup enabled, mode 4
> - // Set LCLK to output, no pull-type and disabled, mode 0
> - SCM_REG(PADCONFS_GPMC_NCS7) = 0x0000001C; // LCD_BKL_X[15:0], LCLK(or GPIO_59)[31:16]
> -
> - // Set LCD pads to outputs, pull-type = up, pullud disabled, mode 0
> - SCM_REG(PADCONFS_DSS_PCLK) = 0x00100010; // LCD_PCLK_X[15:0], LCD_HS_X[31:16]
> - SCM_REG(PADCONFS_DSS_VSYNC) = 0x00100010; // LCD_VS_X[15:0], LCD_OE_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA0) = 0x00100010; // LCD_B0_X[15:0], LCD_B1_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA2) = 0x00100010; // LCD_B2_X[15:0], LCD_B3_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA4) = 0x00100010; // LCD_B4_X[15:0], LCD_B5_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA6) = 0x00100010; // LCD_G0_X[15:0], LCD_G1_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA8) = 0x00100010; // LCD_G2_X[15:0], LCD_G3_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA10) = 0x00100010; // LCD_G4_X[15:0], LCD_G5_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA12) = 0x00100010; // LCD_R0_X[15:0], LCD_R1_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA14) = 0x00100010; // LCD_R2_X[15:0], LCD_R3_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA16) = 0x00100010; // LCD_R4_X[15:0], LCD_R5_X[31:16]
> -
> - // Set D_TXD for output and D_RXD for input. Set both to pullup enabled and mode 1
> - SCM_REG(PADCONFS_MCBSP3_CLKX) = 0x01190019; // D_TXD[15:0], D_RXD[31:16]
> -
> -#ifdef AD7843_GPIOMODE
> - // Depending on AD7843_GPIOMODE setting, we either configure the SPI
> - // interface to the AD7843 as a real SPI device using the OMAP's SPI
> - // controller, or we set it up with GPIO bits...
> - SCM_REG(PADCONFS_DSS_DATA18) = 0x00040004;
> - SCM_REG(PADCONFS_DSS_DATA20) = 0x00040104;
> -#else
> - SCM_REG(PADCONFS_DSS_DATA18) = 0x0002011A; // SPI1_CLK_X[15:0], SPI1_MOSI_X[31:16]
> - SCM_REG(PADCONFS_DSS_DATA20) = 0x001A011A; // SPI1_MISO_X[15:0], *SPI1_CS0_X[31:16]
> -#endif
> -
> - // Set PIRQ for ADS7843 touch interrupt. Set both to pullup enabled and mode 4
> - SCM_REG(PADCONFS_MMC1_DAT4) = 0x01040104; // *I2C_INT_X[15:0], *PIRQ_X[31:16]
> -
> - // GPIO1 is the push button on CSB703(set as input), GPIO0 is is LED on CSB703(set as output)
> - SCM_REG(PADCONFS_MMC1_DAT6) = 0x01040004; // GPIO0_X[15:0], GPIO1_X[31:16]
> -
> - // Set E_INT* to be an input in GPIO mode
> - SCM_REG(PADCONFS_GPMC_WAIT2) = 0x011C011f; // NA[15:0], E_INTX[31:16]
> -
> - // Set SYS_CLKOUT1 for USB_CLK
> - SCM_REG(PADCONFS_SYS_OFF_MODE) = 0x0000010f; // OFF_MODE_X[15:0], SYS_CLKOUT1[31:16]
> -
> - // Set SYS_CLKOUT2 for debug purposes
> - SCM_REG(PADCONFS_SYS_NIRQ) = 0x0000011f; // FIQ[15:0], SYS_CLK2[31:16]
> -
> -}
> -
> -int
> +/* devInit():
> + * As a bare minimum, initialize the console UART here using the
> + * incoming 'baud' value as the baud rate.
> + */
> +void
> devInit(int baud)
> {
> - // Initialize pads
> - pads_init();
> -
> - // Disable MPU Watchdog WDT2
> - WD2_REG(WD_WSPR) = 0x0000aaaa;
> - wait_for_command_complete(WD2_BASE_ADD);
> - WD2_REG(WD_WSPR) = 0x00005555;
> -
> - // Initialize GPIO
> - GPIO_init();
> -
> - // Setup UART pins to UART mode before calling InitUART from uart16550.c
> - UART2_REG(UART_MDR1) = 0x0000;
> - // Initialize the UART
> - InitUART(baud);
> -
> - // Setup CS0 for 110ns Spansion Flash
> - GPMC_REG(GPMC_CS0_CONFIG7) = 0x00000c48; // Base addr 0x08000000, 64M
> - GPMC_REG(GPMC_CS0_CONFIG1) = 0x00001210;
> - //GPMC_REG(GPMC_CS0_CONFIG5) = 0x00080808; // Config5
> -
> - // Setup CS4 for LAN9211, on the CSB740 it is refered to as CS2
> - // and mapped to E_CS
> - GPMC_REG(GPMC_CS4_CONFIG7) = 0x00000F6C; // Base addr 0x2C000000, 16M
> - GPMC_REG(GPMC_CS4_CONFIG1) = 0x00001200;
> -
> - return 0;
> + /* ADD_CODE_HERE */
> }
>
> -/* Referring to table 25-10 of the TRM, install
> - * the RAM exception vectors...
> +/* ConsoleBaudSet():
> + * Provide a means to change the baud rate of the running
> + * console interface. If the incoming value is not a valid
> + * baud rate, then default to 9600.
> + * In the early stages of a new port this can be left empty.
> + * Return 0 if successful; else -1.
> */
> -void
> -ram_vector_install(void)
> +/*int
> +ConsoleBaudSet(int baud)
> {
> - extern unsigned long abort_data;
> - extern unsigned long abort_prefetch;
> - extern unsigned long undefined_instruction;
> - extern unsigned long software_interrupt;
> - extern unsigned long interrupt_request;
> - extern unsigned long fast_interrupt_request;
> - extern unsigned long not_assigned;
> -
> - *(ulong **)0x4020ffe4 = &undefined_instruction;
> - *(ulong **)0x4020ffe8 = &software_interrupt;
> - *(ulong **)0x4020ffec = &abort_prefetch;
> - *(ulong **)0x4020fff0 = &abort_data;
> - *(ulong **)0x4020fff4 = ¬_assigned;
> - *(ulong **)0x4020fff8 = &interrupt_request;
> - *(ulong **)0x4020fffc = &fast_interrupt_request;
> -}
> -
> -void
> -initCPUio()
> + // ADD_CODE_HERE
> + return(0);
> +}*/
> +
> +/* target_console_empty():
> + * Target-specific portion of flush_console() in chario.c.
> + * This function returns 1 if there are no characters waiting to
> + * be put out on the UART; else return 0 indicating that the UART
> + * is still busy outputting characters from its FIFO.
> + * In the early stages of a new port this can simply return 1.
> + */
> +/*int
> +target_console_empty(void)
> {
> - volatile unsigned register cntens;
> - volatile unsigned register usren;
> - volatile unsigned register pmnc;
> -
> - ram_vector_install();
> -
> - /* Do this stuff to enable the cycle counter
> - * (for use by target_timer)...
> - */
> - /* Allow user mode to have access to performance monitor registers:
> - */
> - asm volatile (" MRC p15, 0, %0, c9, c14, 0" : "=r" (usren));
> - usren |= 1;
> - asm volatile (" MCR p15, 0, %0, c9, c14, 0" : : "r" (usren));
> -
> - /* Enable all counters, and reset Cycle counter...
> - */
> - asm volatile (" MRC p15, 0, %0, c9, c12, 0" : "=r" (pmnc));
> - pmnc |= 5;
> - asm volatile (" MCR p15, 0, %0, c9, c12, 0" : : "r" (pmnc));
> -
> - /* Enable all performance counter registers...
> - */
> - asm volatile (" MRC p15, 0, %0, c9, c12, 1" : "=r" (cntens));
> - cntens |= 0x8000000f;
> - asm volatile (" MCR p15, 0, %0, c9, c12, 1" : : "r" (cntens));
> -}
> -
> -/* target_reset():
> - * Set the counter to 16 ticks before trigger, then enable the
> - * watchdog timer (WDT2) and wait...
> + // if (UART_OUTPUT_BUFFER_IS_EMPTY()) <- FIX CODE HERE
> + return(0);
> + return(1);
> +}*/
> +
> +/* intsoff():
> + * Disable all system interrupts here and return a value that can
> + * be used by intsrestore() (later) to restore the interrupt state.
> */
> -void
> -target_reset(void)
> +ulong
> +intsoff(void)
> {
> - // Preload the count-up register...
> - WD2_REG(WD_WCRR) = 0xfffffff0;
> -
> - // Start MPU Watchdog WDT2
> - WD2_REG(WD_WSPR) = 0x0000bbbb;
> - wait_for_command_complete(WD2_BASE_ADD);
> - WD2_REG(WD_WSPR) = 0x00004444;
> + ulong status;
>
> - // Now just wait...
> - while(1);
> + /* ADD_CODE_HERE */
> + return(status);
> }
>
> +/* intsrestore():
> + * Re-establish system interrupts here by using the status value
> + * that was returned by an earlier call to intsoff().
> + */
> void
> -intsrestore(psr)
> -ulong psr;
> +intsrestore(ulong status)
> {
> - putpsr(psr);
> + /* ADD_CODE_HERE */
> }
>
> -/*
> - * Read the program status register (CPSR)
> - * and set the FIQ and IRQ bits.
> +/* cacheInitForTarget():
> + * Establish target specific function pointers and
> + * enable i-cache...
> + * Refer to $core/cache.c for a description of the function pointers.
> + * NOTE:
> + * If cache (either I or D or both) is enabled, then it is important
> + * that the appropriate cacheflush/invalidate function be established.
> + * This is very important because programs (i.e. cpu instructions) are
> + * transferred to memory using data memory accesses and could
> + * potentially result in cache coherency problems.
> */
> -ulong
> -intsoff(void)
> +void
> +cacheInitForTarget(void)
> {
> - ulong psr;
> -
> - psr = getpsr();
> -
> - /*
> - * Set bit 6, bit 7 to disable interrupts.
> - */
> - putpsr(psr | 0x000000c0);
> - return(psr);
> + /* ADD_CODE_HERE */
> }
>
> -/* show_revision():
> - * Called when the system banner is printed...
> +/* target_reset():
> + * The default (absolute minimum) action to be taken by this function
> + * is to call monrestart(INITIALIZE). It would be better if there was
> + * some target-specific function that would really cause the target
> + * to reset...
> */
> void
> -show_revision(int center)
> +target_reset(void)
> {
> - int (*pfunc)(char *, ...);
> - volatile unsigned register main_id;
> - volatile unsigned register silicon_id;
> -
> - if (center)
> - pfunc = cprintf;
> - else
> - pfunc = printf;
> -
> - asm(" MRC p15, 0, %0, c0, c0, 0" : "=r" (main_id));
> - asm(" MRC p15, 1, %0, c0, c0, 7" : "=r" (silicon_id));
> -
> - pfunc("Silicon ID: %d.%d\n",
> - ((silicon_id & 0xf0)>>4),(silicon_id & 0xf));
> -
> - pfunc("CPU Rev: %d, Variant: %d\n",
> - main_id & 0xf,(main_id & 0x00f00000) >> 20);
> -
> - pfunc("CM Rev: %d.%d, PRM Rev: %d.%d\n",
> - CM_REV_MAJ(),CM_REV_MIN(),PRM_REV_MAJ(),PRM_REV_MIN());
> +// flushDcache(0,0);
> +// disableDcache();
> +// invalidateIcache(0,0);
> +// disableIcache();
> + monrestart(INITIALIZE);
> }
>
> -/* target_timer():
> - * Used in conjunction with INCLUDE_HWTMR and TIMER_TICKS_PER_MSEC
> - * to set up a hardware based time base.
> +/* If any CPU IO wasn't initialized in reset.S, do it here...
> + * This just provides a "C-level" IO init opportunity.
> */
> -unsigned long
> -target_timer(void)
> -{
> - volatile unsigned register ccr;
> -
> - asm(" MRC p15, 0, %0, c9, c13, 0" : "=r" (ccr));
> -
> - return(ccr);
> -}
> -
> -/* cacheInitForTarget():
> - Enable instruction cache only...
> -*/
> void
> -cacheInitForTarget()
> +initCPUio(void)
> {
> - asm(" MRC p15, 0, r0, c1, c0, 0");
> - asm(" ORR r0, r0, #0x1000"); /* bit 12 is ICACHE enable*/
> - asm(" MCR p15, 0, r0, c1, c0, 0");
> -
> - /* Flush instruction cache */
> - asm(" MCR p15, 0, r0, c7, c5, 0");
> + /* ADD_CODE_HERE */
> }
> -
> diff --git a/ports/beagleboneblack/cpuio.h b/ports/beagleboneblack/cpuio.h
> index 64ff49c..2021851 100644
> --- a/ports/beagleboneblack/cpuio.h
> +++ b/ports/beagleboneblack/cpuio.h
> @@ -1,76 +1,3 @@
> -//=============================================================================
> -//
> -// cpuio.h
> -//
> -// CPU/Board Specific IO
> -//
> -// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
> -// Date: 05-16-2008
> -// Description: This file contains the IO functions required by Micro Monitor
> -// that are unique to each CPU/Board combination
> -//
> -//
> -// cpuio.h for the CSB740 OMAP3530 Cortex-A8
> -//
> -//=============================================================================
> -
> -// board specific defines for micro monitor
> -#define DEFAULT_BAUD_RATE 38400
> -#define MON_CPU_CLOCK 400000000
> -
> -#define LOOPS_PER_USEC 5
> -
> -#define BASE_OF_NAND 0x1000
> -#define SIZE_OF_NAND 0x100000
> -
> -// SMSC LAN9211 Ethernet
> -#define SMSC911X_BASE_ADDRESS 0x2C000000 // CS4 on OMAP3530 but we call it CS2
> -
> -// LCD Defines
> -//
> -// The LCD frame buffer is fixed at 0x80200000, which is 2Mbyte from the
> -// beginning of SDRAM space. Note that we access it 16-bits at a time.
> -
> -#define LCD_BUF_ADD 0x80200000
> -#define LCD_BUF(_x_) *(vushort *)(LCD_BUF_ADD + _x_) // Frame Buffer
> -#define USE_FONT8X8
> -#define LCD_GET_PIXEL_ADD(_X_, _Y_) (((_Y_ * PIXELS_PER_ROW) + _X_)*2)
> -
> -// defines for the display geometry - OSD043TN24 480x272 TFT
> -// (some of these defines are also used by uMon's frame buffer interface)
> -#define PIXELS_PER_ROW 480 //
> -#define PIXELS_PER_COL 272 //
> -#define BITS_PER_PIXEL 16 //
> -#define PIXFMT_IS_RGB565 1
> -#define FBDEV_SETSTART fbdev_setstart
> -#define FRAME_BUFFER_BASE_ADDR LCD_BUF_ADD
> -#define LCD_H_WIDTH 41 // pulse width in pixels
> -#define LCD_H_FRONT 2 // front porch (sync to enable)
> -#define LCD_H_BACK 2 // back porch (enable to sync)
> -#define LCD_V_WIDTH 10 // pulse width in lines
> -#define LCD_V_FRONT 2 // front porch (sync to enable)
> -#define LCD_V_BACK 2 // back porch (enable to sync)
> -//#define LCD_PCD 2 // LCD PERCLK3 = 32Mhz/PCD +1 = Pixel Clock ~ 4Mhz
> -
> -#define TOP 1
> -#define BOTTOM (PIXELS_PER_COL-1)
> -#define LEFT 0
> -#define RIGHT (PIXELS_PER_ROW-1)
> -#define CENTER_X (PIXELS_PER_ROW/2)
> -#define CENTER_Y (PIXELS_PER_COL/2)
> -
> -#define ROWS_PER_SCREEN 17
> -#define COLS_PER_SCREEN 60
> -
> -#define LCD_BG_DEF 9
> -#define LCD_FG_DEF 15
> -
> -#define LCD_FB_SIZE(_depth_) (((PIXELS_PER_COL * PIXELS_PER_ROW) * _depth_) / 8)
> -
> -#define LCD_ROW_SIZE(_depth_) ((PIXELS_PER_ROW * _depth_) / 8)
> -
> -#define LCD_GET_ADD(_row_, _col_, _depth_) (((((_row_ * PIXELS_PER_ROW) * FONT_HEIGHT) \
> - + (_col_ * FONT_WIDTH)) \
> - * _depth_) / 8)
> -
> +#define DEFAULT_BAUD_RATE 38400
>
> +#define MONARGV0 "umon"
> --
> 2.3.3
>
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