Building RTEMS for an MC68F333
Robin.Kirkham at mlb.dmt.csiro.au
Thu Aug 21 08:35:25 UTC 1997
Chris Johns wrote:
> Robin Kirkham wrote:
> > I'm trying to build an RTEMS BSP for an in-house MC68F333 module. The 68333
> > has a CPU32 core. I thought I'd start with the efi332 BSP and work from there.
> > During the compile it complains ... HOW DO I INSTALL THE INTERRUPT STACK!!!.
> > This warning comes from c/src/exec/score/cpu/m68k/cpu.c. The CPU32 indeed
> > has no separate interrupt stack.
> My understanding is the CPU32 is a kind of 020 with-out bit field instructions. I
> would therefore assume it has a VBR register (the 68340 has one). This warning is
> generate for 68000 processors only. I would check your configuration.
I am compiling using m68k-gcc -m68332. You're right about what the CPU32 is.
The CPU32 does have a VBR; the 68000 is about the only one that does not.
However, this problem does not relate to the VBR, but the existance or
otherwise of a separate stack pointer for interrupts. The issue is, does
> Is this CPU32 core the same one used on the 68360 (QUICC) and 68340 ?
> If it is then take a look at the configuration for the gen68360 BSP. It might be a
> better match.
As I understand things, it is the same CPU32 core as is found in the 68332,
340, 360, and others, unless Motorola are using CPU32 to mean "any slightly
683xx-ish thing". I don't think they do that.
I'll have a look at the other BSPs tomorrow, but my reading of the CPU
feature stuff in m68k.h makes me think it won't solve the problem (if indeed
there is one).
Robin Kirkham CSIRO Manufacturing Science and Technology
Project Engineer Locked Bag 9, Preston 3072, Australia
robin.kirkham at mlb.dmt.csiro.au Phone: +61 3 9662-7756 Fax: +61 3 9662-7853
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