LTP BDM interface

Erwin Rol 320094152587-0001 at
Fri Jun 2 11:25:53 UTC 2000

Hello Frank,

I have found something "interesting" in your LPT BDM interface.
The Freeze lines on the BDM port double as VFLS[0-1] lines (on the
that is , dunno about other PowerPC cpu's). When the CPU goes into debug
mode the VFLS[0-1] lines both go to '1' but 00 01 and 10 have a
meaning (See page 37-3 of the MPC860 PowerQUICC User's Manual) and in
your hardware you only test one of the two lines which may cause a false 
positive recognition of the debug mode. A simple solution might be
a AND port to "mix" the two lines in hardware, because this is always 
what we want and we aren't interested in the other functions of

Does anybody else use Frank's hardware interface and GDB patches and has 
strange problems like the debugger stopping the target at random places

- Erwin

        Q - S O F T - E N G I N E E R I N G 
     Rodachtalweg 11, 81549 Muenchen, Germany

Erwin Rol (Software Engineer)     phone: +49-89-68050051
Erwin.Rol at  fax  : +49-89-68050052

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