Context switching

[Silverio Diquigiovanni]

> "Jimen.Ching" wrote:
> 
> I have a question about context switching.  I'm looking through the
> code and see that a context switch may be attempted in
> rtems_clock_tick if dispatching is enabled.
> But rtems_clock_tick is called from inside an interrupt handler.
> Thus, _Thread_Dispatch_disable_level is always greater than zero,
> and the context switch is never done.
> 
> Did I miss something?  I'm trying to use timeslicing, 100 ticks per
> slice, but it doesn't seem to work.

You could have missed the setting of RTEMS_TIMESLICE property in task
Mode. If you have someone of your tasks with RTEMS_NO_PREEMPT or with
a major priority the mechanism of timeslicing could be stopped when
this task go in "execute" state.

In reference to thread dispatcher called under an ISR, 
how in rtems_clock_tick, remember which in the context switch are 
restored all states of resuming task including his value of interrupt
level.

Example:

  +
  |
  | Time
  |
  V

  +-------------+
  |             |
  |    TAU1     |
  |             | (1)
  +-------------+ ----------> +-------------+
                              |    ISR      |
  +-------------+ <---------- +-------------+ <- rtems_clock_tick()
  |             |          (2)
  |    TAU2     |
  |             | (3)
  +-------------+------------>+-------------+
                              |    ISR      |
  +-------------+ <---------- +-------------+ <- rtems_clock_tick()
  |             |          (4)
  |    TAU1     |
  |             |
  +-------------+ ---.... and so again

- We have only 2 tasks with RTEMS_TIMESLICE in Task Mode.
- We have 1 tick for timeslice so rtems_clock_tick always invoking
  the thread dispatcher.
- Task 1 and 2 have the interrupt level fixed to 0.
  (They could be have different interrupt levels).
- ISR, in this case the Clock Manager, which call rtems_clock_tick()
  directive, must have the interrupt level always higher of the major
  interrupt level of all tasks, in this case 2.
- In RTEMS the interrupt level 0 is lower and 255 is higher.
  (The higher level is CPU dependent, in case of Hitachi SH-1 is 15).

01) TAU1 start his work.
02) The end of clock elapsed timer invoke the ISR of Clock Manager (1),
    and the new, ISR, priority level is setted (automatically by CPU).
03) The task context of TAU1 is saved (included interrupt level
    automatically saved by CPU in stack before go to ISR).
04) All jobs of Clock Manager is performed.
05) At the end of ISR the rtems_clock_tick() is invoked (2).
    Inside the rtems_clock_tick the timeslicing manager restore the
    context of TAU2 task and automatically the flow continue in it.
06) TAU2 continue his work.
07) And so again....


Good Work !
Silverio Diquigiovanni