Q powerpc new exception processing.

[Eric Valette]

Sergei Organov wrote:

> > As the author of the code, I think it is time to jump in. My credo about
> > the way Exception/Interrupt handling must be coded is :
> >       - Exception are processor dependent (CPU common),
> >       - Interrupt handling is board dependent (BSP),
> 
> Until processor is actually microcontroller that has its own PIC. In which
> case interrupt handling (at least interrupts dispatching) could be considered
> processor dependent.

Note quite true : take example of MPC860, you can physically route
interrupt on the SIU.
> 
> Also, decrementer seems to be common to most (all?) of PowerPC processors,
> so what's the reason to mix its handling with external interrupts that indeed
> are different between processors/boards?

Because anyway interrupt are a state machine that require sharing :
	- Interrupt nesting level (in the case of PPC SRR0, SRR1),
	- not enabling interrupts in the meedle of another interrupt path were
they are disabled...

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