Q powerpc new exception processing.

[Eric Valette]

Eric Valette wrote:
> 
> Sergei Organov wrote:
> 
> > > As the author of the code, I think it is time to jump in. My credo about
> > > the way Exception/Interrupt handling must be coded is :
> > >       - Exception are processor dependent (CPU common),
> > >       - Interrupt handling is board dependent (BSP),
> >
> > Until processor is actually microcontroller that has its own PIC. In which
> > case interrupt handling (at least interrupts dispatching) could be considered
> > processor dependent.
> 
> Note quite true : take example of MPC860, you can physically route
> interrupt on the SIU.

I think there are too many untold things with this sentence and will try
to complete myself. If you look at the interrrupt architecture of a
motorola mbx860 board, and want to handle correctly PCI or IDE
interrupts, you have to know where on the SIU the thundra PCI bridge
interrupt and legacy IO interrupts have been hardwired. Og course you
can virtualize interrupt handling for IO risk co-processor but not for
external peripherals.

==> If you want an interrupt handing scheme for MPC860, it must also be
board dependent. You can probably share most of the code for IO risk
co-processor but need to creafully define you interrupt mask and
priorities to achieve desired interrupt latency.

Hope it clarifies my point a little bit further...

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