MMU Page table support for RTEMS

[tom_armistead]

Hi,

    I am working with RTEMs on PowerPC boards.  RTEMs for PowerPC uses
the PPC BATs for mapping of address space but unfortunately, BATs cannot
address all of the address space needed for the boards that I am working
with (1 Gig+ of RAM).

   So, I am preparing to add page table support to PowerPC RTEMs to
increase the address range that I can map (and to allow setting of
attributes at the page level).

 First, has anyone already done this?  I'd rather not reinvent the wheel
if it already exists.

Second, would it be worthwhile to add hooks at the highest CPU level so
that other CPU architectures could add their own implementation of the
functions (similar to the way the cache functions work in libcpu)?  I
don't know enough about other CPU architectures to actually implement it
for them but I could put in hooks to allow others to easily do so.  Or
would it be better to keep this code at the PowerPC specific CPU level?

Thanks,
Tom Armistead
tom_armistead at phx.mcd.mot.com