MMU Page table support for RTEMS

[VALETTE Eric]

tom_armistead wrote:

 
>     I am working with RTEMs on PowerPC boards.  RTEMs for PowerPC uses
> the PPC BATs for mapping of address space but unfortunately, BATs cannot
> address all of the address space needed for the boards that I am working
> with (1 Gig+ of RAM).


What a amount of memory!!! A high-end project I suppose :-)


>  First, has anyone already done this?  I'd rather not reinvent the wheel
> if it already exists.


For powerpc no. For Intel yes because of lack of decent cache flush 
instruction for PCI devices registers handling...

NB : the MCP750 boot loader (written not be me but by Gabriel Paubert) 
does enable pagination if I remember correctly. The MCP750 code (I 
wrote) use only the BAT as you mentionned eralier.



> Second, would it be worthwhile to add hooks at the highest CPU level so
> that other CPU architectures could add their own implementation of the
> functions (similar to the way the cache functions work in libcpu)?  I
> don't know enough about other CPU architectures to actually implement it
> for them but I could put in hooks to allow others to easily do so.  Or
> would it be better to keep this code at the PowerPC specific CPU level?


Depends what you want to do with the MMU mapping. If you keep the 1-1 
mapping and do not implement U/S proctection, we could probably define 
something to
	1) establish one/one mapping for chunk of memory,
	2) manipulate page attribute like setting protection (RWX),
	3) and caching atttribute (ON/OFF/Writethrough/Copyback) for chunk of 
memory aligned on pages boundary.

I think joel could elaborate more...

My 0.02$






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