Interrupt latency problems on MPC860

[Phil Torre]

On Wed, Nov 14, 2001 at 02:49:06PM -0600, Joel Sherrill wrote:
> 
> Moreover, this really may be tough to attain on the PowerPC
> architecture without VERY special care.  The PowerPC by default does
> not really have interrupt priority or (without work) nesting of 
> interrupts.  So all you have to do is take > 79 usecs to process
> an interrupt and you are nailed.  Since (I am pretty sure about this)
> interrupts are disabled from the time a handler is vectored by HW
> until the entire ISR returns, you have a long window there.  

Originally, this was the case.  There is a comment in irq_stub.S,
right after _ISR_Nest_level is incremented, which says "From here on
out, interrupts can be re-enabled. RTEMS convention says not".  I
added an instruction there to re-enable interrupts by setting MSR[EE],
but it seems to make no difference.

Am I right in thinking that there should only be two times when maskable
interrupts are disabled:  In between the hardware vector and nesting,
and in between rtems_interrupt_disable() and rtems_interrupt_enable()?

Thanks,
-Phil

-- 

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Phil Torre                               phone: 425-820-6363 x234
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