MIPS BSPs

[araes]

Wayne,
Your conclusions seem appropriate and reasonable.  I currently have designs
with three different MIPS CPU's.  I am using NEC's Vr5432, QED's RM5231A and
PMC-Sierra's RM7000A all have the MIPS IV ISA but all have uniquely
different interrupt, TLB and specialized Embedded, DSP and Multimedia
instructions and enhancements.

I have been grappling with how to modify the current build system to
accommodate the different processors.  Each CPU is targeted at a different
project with different requirements and I am happy with these CPU choices.
Now I have to incorporate my other choice to use RTEMS.

I have been feeling that a complete architectural re-mapping of RTEMS (for
true 64-bit use) is required in order to take advantage of what the 64-bit
MIPS architecture is intended to provide.

Charles L. Nelson
Embedded System Architects
URL - www.embsyspro.com

P.S.
Notice that I said "re-mapping" and not "re-design".  So don't flood me with
hate mail. :)

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