joel.sherrill at OARcorp.com
Sat Oct 13 15:55:23 UTC 2001
> Your conclusions seem appropriate and reasonable. I currently have designs
> with three different MIPS CPU's. I am using NEC's Vr5432, QED's RM5231A and
> PMC-Sierra's RM7000A all have the MIPS IV ISA but all have uniquely
> different interrupt, TLB and specialized Embedded, DSP and Multimedia
> instructions and enhancements.
The general overriding design philosophy is that the score/cpu code
only depends on mips ISA level. If a "executive core routine" can't
be implemented under that restriction, then is goes in libcpu. For
example, the entire interrupt dispatching for the SH is placed in
libcpu. Another example is that from the executive's viewpoint,
the maximum number of vectors on the mips port is variable based upon
the contents of a variable initialized (constant) by the CPU model
This goal is fundamentally critical for RTEMS to be able to provide
a BSP Kit model. The executive proper has to be provided like
libc.a -- in the form of a multilib'ed library. Look at the
variants of libc for the toolset you are using -- that is all
we can depend on in score/cpu.
> I have been grappling with how to modify the current build system to
> accommodate the different processors. Each CPU is targeted at a different
> project with different requirements and I am happy with these CPU choices.
> Now I have to incorporate my other choice to use RTEMS.
If something is in score/cpu that violates the rule, then it needs to
> I have been feeling that a complete architectural re-mapping of RTEMS (for
> true 64-bit use) is required in order to take advantage of what the 64-bit
> MIPS architecture is intended to provide.
I don't doubt that but the mips port has some items on the mips
already at least partially addressed. For example, the size of
the registers is conditional based on the mips ISA level.
> Charles L. Nelson
> Embedded System Architects
> URL - www.embsyspro.com
> Notice that I said "re-mapping" and not "re-design". So don't flood me with
> hate mail. :)
This is my idea as well. It is only a matter of fune-tuning specific
issues. Things that vary more than the score/cpu code accounts for.
No big deal as long as we do it issue/varying feature at a time.
Joel Sherrill, Ph.D. Director of Research & Development
joel at OARcorp.com On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
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