FW: MIPS BSPs

[Wayne Bullaughey]

> -----Original Message-----
> From: joel at wmi.com [mailto:joel at wmi.com]On Behalf Of Joel Sherrill
> Sent: Monday, October 15, 2001 1:49 PM

Something about the email headers you send get translated by our mail server
to be from a joel here at WMI.

> Because the ultimate goal is to be able to provide a prebuilt
> RTEMS (ala libc.a) that is augmented by a BSP Kit to be specific
> to your hardware.  At that point, libcpu and libbsp will be
> foundation of the BSP Kit the main things a user builds locally.
> Everything else will have been prebuilt.
>

I hadn't understood what you meant by this before. I now see the problem
in the solution I was suggesting.

> There is a documented classification now "RTEMS_CPU_MODEL" which is
> used in the libcpu code to distinguish which set of code to use
> to augment the basic CPU port. libcpu already includes cache
> management and interrupt vectoring code for the mips.
>

Where is this documented?

> The ISA is not completely hidden because there are issues of
> branch delay, register sizes (to save/restore), FPU presence/abscence,
> etc. This covers most of the code in score/cpu.  Interrupt dispatching
> and cache management tend to be CPU model dependent so we have
> that in libcpu.
>

I don't think FPU presence can be determined from ISA. There probably should
be a function that returns TRUE if it exists. libcpu would supply the
function or maybe libbsp.

Wayne Bullaughey               Voice:  (610) 692-9526 ext: 104
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