MIPS BSPs

[Wayne Bullaughey]

Some of the problems I've been trying to solve to handle the IDT 32364 can
be solved if conditional compilation based on __mips == 2 is added.
According to "See MIPS Run" by Dominic Sweetman the ISA II was originally
used for the MIPS 6000. I don't think RTEMS needs to support the 6000.
Sweetman goes on to say that ISA II is now the choice for 32 bit processors
which have coprocessor 0 registers like typical ISA III and IV processors.
This would solve two problems in the exec/score/cpu/mips code.

The return from interrupt instruction is different in ISA I (rfe) and ISA II
and III (eret). And the bits in the status register for interrupt enable.
ISA I processors used SR_IEC. ISA II and later use SR_EXL and SR_IE versus.
The ISA designation does not really define these attributes but from the
processors I'm aware of they hold.

Wayne Bullaughey               Voice:  (610) 692-9526 ext: 104
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