MIPS BSPs

[Wayne Bullaughey]

Attach is my proposal for a replacement for exec/score/cpu/mips/idtcpu.h. I
suggest calling it exec/score/cpu/mips/mipscpu.h. The current idtcpu.h can
be left as is so BSP code depending on it will not break. The changes I mode
include:

Removing definitions that were too CPU specific to be conditionally compiled
based on the __mips level.

Added conditions for __mips == 2 which correspond to IDT 32364. IDT 32364 is
a 32 bit processor that is a lot more like 64 bit processors in register
layout and instruction set then the earlier 32 bit processors. These
definitions may or may not apply to other newer 32 bit processors. If not
these definitions may not be appropriate in this file.

Added an OFFSET parameter to the interrupt vector macros so that
they can be located at either the boot vector location or the standard
location. These macros are not used in exec/score/cpu/mips files. They
typically are used in libbsp startup code. The value of the OFFSET parameter
is BSP specific.

Rearranged the status register bit definitions so there is only one copy of
common definitions.

Reorganized the coprocessor register definitions into __mips == 1 and __mips
> 1 and added a section __mips == 2 which has defines for IDT 32364.

If this seems reasonable I will make similar proposals for the other files
in exec/score/cpu/mips.

Wayne Bullaughey               Voice:  (610) 692-9526 ext: 104
Woodward McCoach, Inc.                 (877) 284-4804
1180 McDermott Drive           Fax:    (610) 436-8258
West Chester, PA 19380         Email:  wayne at wmi.com
                               web:    www.wmi.com
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