PowerPC exception processing (was Fwd: RTEMS pthreads performance)

[Kamen Penev]

Joel Sherrill wrote:
> Kamen Penev wrote:
>
> How different would that board be from an mpc8260ads?  That has a BSP
> in the current tree.

Yes, I am aware of the 8260 bsp. Both the 8260 and the 8245 are integrated
devices that include the same PowerPC G2 core, but different peripherals,
program interrupt controllers and miscellaneous other logic. In our case
RTEMS will be running on top of DINK32 (Motorola's debug monitor for
Sandpoint and Excimer boards), which does the hardware initialization for me
(that's why the psim target was a very close match for me).  I will probably
use the 8260 bsp as a starting point. Most likely, there will be more to
remove than to add.



I think the following paragraphs are a great candidate for a README file in
cpukit\score\cpu\powerpc\rtems and/or for the "Interrupt Processing" chapter
of the PowerPC supplement.

> The old exception processing model basically did
> not attempt to integrate the interrupt controllers into the interrupt
> management.  It treated the PowerPC as a CPU with weak interrupt
> skills (which it is IMO). But since the PowerPC is almost always tied to
an external interrupt
> controller, it can be logically treated as an extension of the CPU and
that is the
> core of the difference between the old and new exception processing
> models.
> The old exception processing code is still in there because the 4xx
> BSPs and some 6xx BSPs have not been converted.  Converting those BSPs
would be
> not only time-consuming but require testing so it has been done on a
> piecemeal basis.

Thanks for your help!

Kamen