Fwd: RTEMS pthreads performance (was RTEMS vs other realtimeOperating Systems ..)

[Valette Eric]

Joel Sherrill wrote:

> First I would love to see psim converted to the new exception processing
> model.  The old exception processing model basically did not attempt to
> integrate the interrupt controllers into the interrupt management.  It
> treated the PowerPC as a CPU with weak interrupt skills (which it is
> IMO).
> But since the PowerPC is almost always tied to an external interrupt
> controller,
> it can be logically treated as an extension of the CPU and that is the
> core of the difference between the old and new exception processing
> models.

IMHO : there is no old PPC *exception processing* in fact :-) There is 
some old interrupt management code for PPC.

I know exceptions and interrupts handling are usually mixed but this is 
an error because :
	- the exceptions are BSP independent. There are part of the data book 
of the processor and are therefor only CPU dependent,
	- On most processor with a a single IRQ line, you have external 
hardware to manage to handle the irq (and in particular multiplex and 
prioritize them). Sometimes it is normalized (e.g PPC with OpenPIC, ix86 
with dual 8259 emulation or APIC)

The real goal of the x86 and PPC exception code is really to handle 
exceptions as it is very usefull for :
	1) debugging crash via register dump,
	2) Implement rdbg,
	3) use some registers to handle hardware breakpoints or things 
generating excpetions.

Sometimes (Frequently but not always) an IRQ is just a particular 
exception like on PPC and the two code (IRQ/EXCEP) have some 
interactions. But they are handled differently on some other (e.g ix86, 
68030, ...)

On top of that, I found the IRQ handling API, not satisfactory because 
not handling priorities on such external IRQ mgt hardware. IRQ 
Priorities are handled on ix86, could be on 6/7xx PPC (just the code to 
program the priority in the openpic is missing). On 8XX, I used a static 
table with no interface to change priorities but this could esasily been 
done. The API as it is being BSP dependent, you can modify it to take 
full advantage of your IRQ management hardware if you wish.


My 0.02 $



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