MSR storing - to Joel and E.Valette

[leonp]

On Thursday 24 January 2002 11:53, you wrote:
> leonp wrote:
> > In general -  IMHO, the MSR is the MACHINE state register. I looked
> > through all it bits once more and didn't find one that seems to be thread
> > relative.
> Do you think floatting point attribute is no a thread attribute or that
> single stepping is not also a thread attribute?
About FP - the MPC860 has no FPU. The only one FP related bit in MSR is FPU 
enable. Here is this bit definition in user's manual:
"Floating-point available. 
0 The processor prevents dispatch of floating-point instructions, including 
floating-point loads, stores, and moves. 
1 The processor can execute floating-point instructions. (This setting is 
invalid on the MPC860) "

About SS - the SS bit allows stepping one machine instruction only. The CPU 
will not be able to make context switch in this mode. Besides, if I am doing 
SS, what I want is really SS, I want to execute precisely one instruction. So 
this bit seems for me also not tread relevant.


> I know applications that want to run with irq disabled but suspend
> themselves waiting for hardware events... You would not be able to to this.
This I didn't catch. How will they know about HW events, if IRQ is disabled?

Thanks.
-- 
leonp at plris.com