MSR storing - to Joel and E.Valette

[VALETTE Eric]

Leon Pollak wrote:


>>Why do not use the external hardware controller? You can disable all
>>interrupts at SIU level just by clearing or setting to 0xffffffff in a
>>32 bits word. For me this is the right way to do. But, from a
>>theoritical design point of view, if you manipulate this kinds of bits
>>with selective values (nor everything on or off) at thread level, then
>>you should make the thread non-preemptible...
>>
> OK, but here it seems to me we have some inconsistency.
> From one side saving MSR at a context switch we want to reach IRQ state per 
> thread.
> From another side, the current interrupt priority level is set in SIU, but it 
> seems to be not saved in context.


Because it is never manipulated by threads, just once at system init and 
by non preemptible irq code that is not bound to thread by definition.


> This means, if I have not missed something,  that Joel's goal to preserve the 
> interrupt level per thread remains unimplemented.

I still think your proposed design is broken but I give you a way to 
make a workaround to implement it without breaking other code that may 
make assumption that irq level is per thread and that while making a 
context switch to a thread with irq enabled will reenable the 
interrupts. BTW this is the assumption made by actual rtems init code to 
reenable interrupts when threads are ready to run while doing the first 
context switch.

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