MSR storing - to Joel and E.Valette

[Leon Pollak]

On Thursday 24 January 2002 14:05, you wrote:
> leonp wrote:
> > On Thursday 24 January 2002 12:32, you wrote:
> > But what to do in my case - I want to disable IRQ globally, I don't want
> > HW events to occur?
> Why do not use the external hardware controller? You can disable all
> interrupts at SIU level just by clearing or setting to 0xffffffff in a
> 32 bits word. For me this is the right way to do. But, from a
> theoritical design point of view, if you manipulate this kinds of bits
> with selective values (nor everything on or off) at thread level, then
> you should make the thread non-preemptible...
OK, but here it seems to me we have some inconsistency.
>From one side saving MSR at a context switch we want to reach IRQ state per 
thread.
>From another side, the current interrupt priority level is set in SIU, but it 
seems to be not saved in context.
This means, if I have not missed something,  that Joel's goal to preserve the 
interrupt level per thread remains unimplemented.

-- 
Dr.Leon M.Pollak
Director
PLR Information Systems Ltd.
leonp at plris.com