Can one BSP support multiple memory maps?

Fernando RUIZ CASAS (E-mail) fernando.ruiz at ctv.es
Thu Mar 7 14:31:41 UTC 2002


My 2 cents.

For my sh1 bsp.

--------------------
linkcms.ram
--------------------
/*
 * This is an adapted linker script from egcs-1.0.1
 *
 * Memory layout for an SH 7032 with main memory in area 2
 * This memory layout it very similar to that used for Hitachi's
 * EVB with CMON in rom
 *
 * NOTE: The ram start address may vary, all other start addresses are fixed
 *       Not suiteable for gdb's simulator
 *
 *  Authors: Ralf Corsepius (corsepiu at faw.uni-ulm.de) and
 *           Bernd Becker (becker at faw.uni-ulm.de)
 *
 *  Modified: Fernando RUIZ CASAS (fernando.ruiz at ctv.es)
 *
 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 *
 *  COPYRIGHT (c) 1998.
 *  On-Line Applications Research Corporation (OAR).
 *  Copyright assigned to U.S. Government, 1994.
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id: linkcmds,v 1.1 1998/03/20 17:16:31 joel Exp $
 */

OUTPUT_FORMAT("coff-sh")
ENTRY(_start)

MEMORY
{
  rom           : o = 0x00000000, l = 512k
  flash         : o = 0x00080000, l = 512k
  ram           : o = 0x0A000000, l = 512k

  onchip_ram    : o = 0x0f000000, l = 8k
}

SECTIONS
{
  /* boot vector table */
  .romvect 0x00000000 (NOLOAD): {
    *(romvects);
  } > rom
  .mflash  0x0080000 (NOLOAD):
  {
    *(.flash);
  } > flash

  _ramstart = 0x0A000000 ;

  /* monitor vector table */
  .ramvect   0x0A000000 (NOLOAD) : {
    *(.ramvects);
  }

  /* Read-only sections, merged into text segment: */

  .code 0x0a008000:
  {
    _code = .;
    *(.text)
  } > ram
  _etext = .;
  _mcode = .;
  _ecode = .;
  _mdata = . ;

  .mdata  ALIGN(4) :
  {
    _data = . ;
    *(.data)
  } > ram
  .ctors  .       :
  {
    ___ctors = .;
    *(.ctors)
    ___ctors_end = .;
  }
  .dtors  .       :
  {
    ___dtors = .;
    *(.dtors)
    ___dtors_end = .;
  }
  _edata  =  .;
  __bss_start = .;
  .bss    ALIGN(4) :
  {
   *(.bss)
   *(COMMON)
  } > ram
  _end = . ;

  _HeapStart = . ;
  _HeapEnd  = _HeapStart  + 128 * 1024;

  _WorkSpaceStart = _HeapEnd   ;
  _WorkSpaceEnd  = 0x0a100000 ;

/* The rtc multiplexed area 6 address BYTE bus width */
  _rtc_adr = 0x06000000 ;

  _CPU_Interrupt_stack_low  = 0x0f000000 ;
  _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;

  .stack 0x0f001ff0 (NOLOAD): {
	  _stack = .; *(.stack)
  } > onchip_ram
  /* These must appear regardless of  .  */
}

------------------------
linkcmds.rom
------------------------
/*
 * This is an adapted linker script from egcs-1.0.1
 *
 * Memory layout for an SH 7032 with main memory in area 2
 * This memory layout it very similar to that used for Hitachi's
 * EVB with CMON in rom
 *
 * NOTE: The ram start address may vary, all other start addresses are fixed
 *       Not suiteable for gdb's simulator
 *
 *  Authors: Ralf Corsepius (corsepiu at faw.uni-ulm.de) and
 *           Bernd Becker (becker at faw.uni-ulm.de)
 *
 *  Modified: Fernando RUIZ CASAS (fernando.ruiz at ctv.es)
 *
 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 *
 *  COPYRIGHT (c) 1998.
 *  On-Line Applications Research Corporation (OAR).
 *  Copyright assigned to U.S. Government, 1994.
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id: linkcmds,v 1.1 1998/03/20 17:16:31 joel Exp $
 */

OUTPUT_FORMAT("coff-sh")
ENTRY(_start)

MEMORY
{
  rom           : o = 0x00000000, l = 512k
  flash         : o = 0x00080000, l = 512k
  ram           : o = 0x0A000000, l = 512k

  onchip_ram    : o = 0x0f000000, l = 8k
}

SECTIONS
{
  /* boot vector table */
  .romvect 0x00000000 : {
    *(romvects);
  } > rom

  .code :
  {
    _code = .;
    *(.text)
  } > rom
  _etext = .;
  _mcode = .;
  _ecode = .;
  _mdata = . ;

  .mflash  0x0080000 (NOLOAD):
  {
    *(.flash);
  } >flash

  /* monitor vector table */
  .ramvect  0x0A000000  (NOLOAD) : {
    _ramstart = . ;
    *(.ramvects);
  }

  .mdata  ALIGN(4) :
       AT( ADDR(.code)+ SIZEOF(.code) )
  {
    _data = . ;
    *(.data)
    ___ctors = .;
    *(.ctors)
    ___ctors_end = .;
    ___dtors = .;
    *(.dtors)
    ___dtors_end = .;
  } > ram

  _edata  =  .;
  __bss_start = .;
  .bss    ALIGN(4) :
  {
   *(.bss)
   *(COMMON)
  } > ram
  _end = . ;

  _HeapStart = . ;
  _HeapEnd  = _HeapStart  + 128 * 1024;

  _WorkSpaceStart = _HeapEnd   ;
  _WorkSpaceEnd  = 0x0a080000 ;

/* The rtc multiplexed area 6 address BYTE bus width */
  _rtc_adr = 0x06000000 ;

  _CPU_Interrupt_stack_low  = 0x0f000000 ;
  _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;

  .stack 0x0f001ff0 (NOLOAD): {
	  _stack = .; *(.stack)
  } > onchip_ram
  /* These must appear regardless of  .  */
}

------------------------------------------------------------------

And HERE the trick to choose the option in

   make MTARGET=ram
or
   make MTARGET=rom
or
   make MTARGET=romram  (rom ramloaded (mirror because the ram is 16 bits
bus width))

-----------------------------------------

#
#  ple769.cfg
#
#  default configuration for Hitachi sh1 processors
#
#  Author: Ralf Corsepius (corsepiu at faw.uni-ulm.de)
#
#  $Id: gensh1.cfg,v 1.27 2001/01/05 13:36:58 joel Exp $
#

# HZ=19660800

include $(RTEMS_ROOT)/make/custom/default.cfg

RTEMS_CPU=sh
RTEMS_CPU_MODEL=sh7032

# This is the actual bsp directory used during the build process.
RTEMS_BSP_FAMILY=ple769

# BSP specific preprocessor flags.
# These should only be used in BSP dependent directories.
# BSP_CPPFLAGS=-DHZ=$(CPU_CLOCK_RATE_HZ)

#
#  This contains the compiler options necessary to select the CPU model
#  and (hopefully) optimize for it.
#
CPU_CFLAGS=-m1

# debug flags: typically none, but we use -O1 as it produces better code
# CFLAGS_DEBUG_V = -O1
CFLAGS_DEBUG_V =

# optimize flag: typically -0, could use -O4 or -fast
# -O4 is ok for RTEMS
CFLAGS_OPTIMIZE_V = -O1

#  This section makes the target dependent options file.

define make-target-options
endef

ifndef MTARGET
MTARGET=ram
endif

LINKCMDS=linkcmds.$(MTARGET)

# The following are definitions of make-exe which will work using ld as
# is currently required.  It is expected that as of gcc 2.8, the end user
# will be able to override parts of the compilers specs and link using gcc.

ifeq ($(MTARGET),ram)
define make-exe
	$(LINK.c) $(AM_CFLAGS) $(AM_LDFLAGS) -qnolinkcmds \
	    -Wl,-Map,$(basename $@).map,-Tlinkcmds.ram \
	    $(LDLIBS) -o $@ \
	    $(LINK_OBJS) $(LINK_LIBS)
	$(NM) -n $@ > $(basename $@).num
	$(SIZE) $@
        $(OBJCOPY) -O binary $(basename $@).exe $(MTARGET).bin -R.romvect \
		                   -R.stack -R.bss -R.ramvect -R.iram
endef
else
ifeq ($(MTARGET),romram)
define make-exe
	$(LINK.c) $(AM_CFLAGS) $(AM_LDFLAGS) -qnolinkcmds \
	    -Wl,-Map,$(basename $@).map,-Tlinkcmds.romram \
	    $(LDLIBS) -o $@ \
	    $(LINK_OBJS) $(LINK_LIBS)
	$(NM) -n $@ > $(basename $@).num
	$(SIZE) $@
        $(OBJCOPY) -O binary $(basename $@).exe $(MTARGET).bin \
		                   -R.stack -R.bss -R.ramvect -R.iram
endef
else
define make-exe
	$(LINK.c) $(AM_CFLAGS) $(AM_LDFLAGS) -qnolinkcmds \
	    -Wl,-Map,$(basename $@).map,-Tlinkcmds.rom \
	    $(LDLIBS) -o $@ \
	    $(LINK_OBJS) $(LINK_LIBS)
	$(NM) -n $@ > $(basename $@).num
	$(SIZE) $@
        $(OBJCOPY) -O binary $(basename $@).exe $(MTARGET).bin \
		                   -R.stack -R.bss -R.ramvect -R.iram
endef
endif
endif

# Miscellaneous additions go here

------------------------------------------------------------------


BRGDS.

Fernando RUIZ CASAS
home:correo at fenando-ruiz.com
work:fernando.ruiz at ctv.es


-----Mensaje original-----
De: cjohns at kiwi.objectivedesign.com.au
[mailto:cjohns at kiwi.objectivedesign.com.au]En nombre de Chris Johns
Enviado el: miercoles, 06 de marzo de 2002 22:22
Para: Phil Torre
CC: RTEMS User List
Asunto: Re: Can one BSP support multiple memory maps?


Joel Sherrill wrote:
>
> FYI I recall some user mentioning a trick to avoid
> duplicating info between the two linker scripts.  Something
> about setting values and including a base linker script.
> Who was that?
>

The trick I use is in the linker command file do something like:

SECTIONS
{
  .text . :
  {
     .....
  }

  .data . :
     AT (ADDR(.text) + SIZEOF(.text))
  {
     .....

  }

  .bss (ADDR(.data) + SIZEOF(.data)) :
  {
     .....
  }
}


Then in the makefile use something like:


  ifdef DEBUG
  ROM_BASE=0x00000000
  else
  ROM_BASE=0xff400000
  RAM_BASE=0x00000000
  endif

    ....

  ifdef DEBUG
  ADDRESS_MAP = -Ttext $(ROM_BASE)
  else
  ADDRESS_MAP = -Ttext $(ROM_BASE) -Tdata $(RAM_BASE)
  endif

    ....

  LFLAGS := -N $(ADDRESS_MAP)

    ....

  $(LD) $(LFLAGS)


I hope you get the idea and I am sure you can change this to meet your
specific needs. I use DEBUG to switch the code between a RAM debug
memory map and the ROM memory map with the one linker script.


--
 Chris Johns, cjohns at cybertec.com.au




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