Is there any Guru who knows why interrupts are disabled in ISR?

[Vivek Vaid]

On Fri, 8 Mar 2002, Leon Pollak wrote:

> Hello Gurus,
>         I shall be very thankful for the explanation of the following moment:
>         I look into PPC code file irq_stub.S routine __ISR_handler I see that 
> all 
> interrupts are disabled almost immediatly. They are reenabled at the end of 
> the ISR, after the user ISR has finished its processing, almost at the point 
> of exit from __ISR_handler.
>         This text contains the comment after the _ISR_NestLevel incrementing:
> "From here on out, interrupts can be re-enabled, RTEMS convention says not".
>         Can somebody explain me why interrupts must be disabled inside the 
> user ISR?
> 
> Thanks.
> 

Hi,

I am not a guru and dont know why the interrupts are disabled in RTEMS in
particular.

But from 8085, or z80, we know that inside
the ISR the interrupt has to be disabled, specifically if it is
level-triggered interrupt. because once u have started servicing the
interrupt, u dont want the external hardware to interrupt for the "Same"
cause. so it prevents re-entry of code, and possible stack overflow if the
isr is too long, and processor hasent disabled the interrupt itself.

maybe in the isr you are talking about, there is some  machine specific
part of code that is not reentrant (or they dont want it to be
re-entrant for some reason).

regards
Vivek

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