Is there any Guru who knows why interrupts are disabled in ISR?

[Leon Pollak]

On Friday 08 March 2002 10:41, you wrote:
> Just a side remark : you speak about a processor or even BSP specific
> implementation without mentionning it. Besides and because I rewrote the
> code for i386/pc386 and powerpc (new_exception_handling), what you say
> is false for those platfor ISR are reanabled at processor level almost
> immediately after around 5 intructions and latter at PIC/SIU level...
> but before caling the handler...

Thank you very much for this clarification - I looked into the code of 
"new_exception_handling" but (may be because I have an old version) didn't 
understand that it already works as I wanted.

Once more, thanks.

-- 
leonp at plris.com