Is there any Guru who knows why interrupts are disabled in ISR?

[VALETTE Eric]

Leon Pollak wrote:
> Hello Gurus,
>         I shall be very thankful for the explanation of the following moment:
>         I look into PPC code file irq_stub.S routine __ISR_handler I see that 
> all 
> interrupts are disabled almost immediatly. They are reenabled at the end of 
> the ISR, after the user ISR has finished its processing, almost at the point 
> of exit from __ISR_handler.
>         This text contains the comment after the _ISR_NestLevel incrementing:
> "From here on out, interrupts can be re-enabled, RTEMS convention says not".
>         Can somebody explain me why interrupts must be disabled inside the 
> user ISR?
> 
> Thanks.
> 

Just a side remark : you speak about a processor or even BSP specific 
implementation without mentionning it. Besides and because I rewrote the 
code for i386/pc386 and powerpc (new_exception_handling), what you say 
is false for those platfor ISR are reanabled at processor level almost 
immediately after around 5 intructions and latter at PIC/SIU level... 
but before caling the handler...

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