RTEMS on MCP750 and MTX-60x, for Eric Valette

[gregory.menke at gsfc.nasa.gov]

Steven Grunza writes:
 > I don't have time to do a thorough analysis here but two issues come to mind:
 > 
 > 1)  The MPC745 (which is a MPC750 without L2 cache) is supposed to be a 
 > drop-in replacement for the MPC603e (with some minor voltage level 
 > differences).  This seems to imply that the MPC603e and MPC745/750 
 > registers are the same...

Agreed, but looking at the respective datasheets, the HID0 register
layout is different.  Some bits exist in both but others do not.  I've
not looked at the MMU yet- but the cache config seems to have
considerable differences.  I don't think it would be problematic to
adjust the HID0 definitions in the cpukit registers.h, but I'd like to
avoid unnecessary changes to things.

 
 > 2)  Keep in mind the IBM contribution to the PowerPC architecture... MSB is 
 > bit 0, LSB is the higher numbered bit.  For a 32-bit register Bit0 is the 
 > MSB and Bit31 is the LSB.
 > 

That makes interpretation simpler.  Figures SOMEBODY just has to do it
differently than everybody else... grumble grumble...

Thanks,

Gregm