RTEMS on MCP750 and MTX-60x, for Eric Valette

gregory.menke at gsfc.nasa.gov gregory.menke at gsfc.nasa.gov
Fri Nov 8 17:13:31 UTC 2002

Valette Eric writes:
 > gregory.menke at gsfc.nasa.gov wrote:
 > > 
 > > Hi Eric, 
 > > 
 > > I'm sending this email thru the list because I don't have a valid
 > > email addres for you;
 > As I have been fired recently, the Canon address is indeed no more 
 > valid. Any interesting job near Rennes (West France) appreciated :-)

I love France, but don't know of employment opportunities there

 > > - In registers.h, you lay out the HID0 bits as leftwards bit shifts,
 > >   but the Motorola docs lay out the bits with LSB leftmost, so the
 > >   shifting looks backwards.  Is this just Motorola being backwards
 > >   with their documentation?
 > This always surprised me. But this is the way it is. Remember that PPC 
 > can be little or big endian. So anyway, depending on the case the doc 
 > may be wrong.

It suprised me too, at least they're consistent.

 > > - More importantly, it looks like the 603e has a different HID0 layout
 > >   than the 750, a number of the bits are defined in different ways,
 > >   and registers.h seems to correspond to the 750.  Are you aware of
 > >   issues like this between the two processors?
 > Yes indeed they are different (at least on the 603, not sure for 604). 
 > This means that the routine namipulating the HID registers should be per 
 > CPU (I haven't any recent rtems code here but they are routine for 
 > indentifying the cpu that can be used in conjunction with a switch 
 > somewhere in libcpu/poowerpc). I though, this was already done that way 
 > but if you have the code handy check with a grep...

The cache config issue manifests in the bootloader but once that runs,
RTEMS comes up fine.  I'm tracking things down now.  It <looks> like
the bootloader is only manipulating the bits common to both
processors.  I did find your cache & mmu bsp setup code that I need to
trace through- I think some 603 conditionals may be needed there.

Successful prep booting is also somewhat contingent on several ppcbug
settings, so I may add bootloader code to sanity test them.  I still
have to get used to ppc assembly & registers...

Interestingly, an RTEMS image that runs on our MTX-603 board also runs
just fine on our MCP-750.  The chipsets are quite similar.


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