Need help with CPU_Context_Switch and ISR_Handler for mips32 processor

[gregory.menke at gsfc.nasa.gov]

Joel Sherrill writes:
 > 
 > 
 > Ivica Mikec wrote:
 > > 
 > > Hi!
 > > 
 > > I need help with CPU_Context_switch and ISR_Handler since the ones
 > > provided with RTEMS do not support mips32 processors. I also noticed that
 > > ISR_Handler in mips branch ends with rfe which is an instruction only for
 > > mips1 class of processors. ISR_Handler in mips64orion is in similar state.
 > > Some of the constants are hardcoded for 64 bit. I also don't understand
 > > how it calls my interrupt handler. Can you help me with these issues?
 > 
 > I don't understand what source you are looking at.  What version of
 > RTEMS
 > are you looking at?  The mips port had a thorough reworking over a year
 > ago
 > and works great on R3000 class CPUs now.
 > 

The mips support is known to work on at least 1 R3000 system as well
as at least one MIPS simulator, and <should> be working on R4000.
What is the revision of your processor?  R4000 processors apparently
use ERET instead of RFE.  I'd be happy to fix it if you've found a
problem.  The interrupt handling code is supposed to be able to handle
at least R3000 & R4000 processors.

ISR_Handler calls your handler by virtue of a vector table.
Generally, each possible interrupt and exception is given a vector
number which the programmer specifies when calling
rtems_interrupt_catch.  The vector numbers are supplied via #defines
in a libcpu .h file.  The vector table itself is of little interest,
it is only an array of pointers.  When the interrupt or exception
occurs, ISR_Handler will call the handler.  The handler should be
written in C.  At this time MIPS interrupts will not nest, however all
interrupts that assert while the ISR vectoring routine runs will be
serviced.

As I understand it, the mips64orion bsp is deprecated.

Gregm