Need help with CPU_Context_Switch and ISR_Handler for mips32 processor

[gregory.menke at gsfc.nasa.gov]

Ivica Mikec writes:
 > >
 > > Joel Sherrill writes:
 > >  >
 > >  >
 > >  > Ivica Mikec wrote:
 > >  > >
 > >  > > Hi!
 > >  > >
 > 
 > Hi!
 > 
 > In my opinion cpu_asm.S is seriously broken for any MIPS processor >
 > mips1. Here is the cpu_asm.S which I modified. It still doesn't work. Can
 > you take a look and give me directions on how to fix it. Most important
 > functions are ISR_Handler and CPU_Context_switch. Main reason for this is
 > SR_EXL bit in status register which must be set to 0 if one wants to
 > enable interrupts. Originaly this was not done properly.

It might well be broken for non-mips1 processors, you may well be the
first to be testing it.  __mips32 as a #ifdef test is incorrect.  Use
__mips1 or __mips3.

What variation of MIPS are you using?  I really must insist on knowing
this before I can be of any help.

Given you suggest SR_EXL as an interrupt enable bit, I infer you are
running on a R4000.  Is this correct?

I have R4000 documentation which I'll use to help track down what is
going wrong, however I really do need to know what processor & bsp
you're using.

Gregm