BSP for MIPS32 4KC

[Joel Sherrill]

mikeci at acm.org wrote:

>>Ivica,
>>
>>I am about to start a BSP for the AMD Au1500 which is MIPS32
>>and I wonder if you have any specific details on the context
>>and interrupt handling changes.  If not, what makes you feel this
>>will be the case?
>>
>>Thanks,
>>Michael
>>
> 
> Michael,
> 
> Take look in $RTEMS_HOME/cpukit/score/cpu/mips. There you have cpu.c and
> cpu_asm.S. Edit cpu_asm.S and search for function _ISR_Handler. You will
> see that this function returns with:
> 
> 	j         k1
> 	rfe
>         NOP
> 
>        .set    reorder
> ENDFRAME(_ISR_Handler)
> 
> This is incorrect for MIP32. rfe instruction is reserved for R3000 and not
> for MIP32.
> 
> This is just one small example. All the files in this dierctory should be
> updated to support MIP32.

When someone has MIPS32 support they have the slightest faith
in, please submit a patch.  If it only introduces new conditional
code and doesn't alter existing code, I am prone to merge it given
that there appear to be multiple testers.

If Greg Menke verifies that it doesn't break the Mongoose, then I
am prone to take more intrusive changes.

> 
> Regards,
> 
> Ivica
> 
> 
> 


-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel at OARcorp.com                 On-Line Applications Research
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