mips: genmongoosev/start/start.S

[Bill Gatliff]

Joel:


> This should be inside the assembler because gcc is directly generating
> lw and st instructions.  The PowerPC also has instructions like this
> and I vaguely recall the PA-RISC assembler doing the same thing. 


Yep.  Greg corrected me shortly after my post, I was getting confused by 
some Linux kernel headers.


Oh, and add ARM to the list:


   ldr     sp, =(__stack_end__ - 0x1000)


The ARM LDR instruction can't take a 32-bit address, so gas synthesizes 
this by doing something like the following:


   ldr r0, 1f
   ...
   1f: .long (__stack_end__ - 0x1000)


You don't see this going on in your .S file, but if you look at an 
objdump output, it becomes readily apparent:


   $ arm-elf-objdump --source crt0.o | less
   ...
       ldr     sp, =(__stack_end__ - 0x1000)
  6c:   e59fd060        ldr     sp, [pc, #96]   ; d4 <halt+0x8>
   ...

[Apologies for the formatting, here's where HTML emails can be handy!]


I'm pretty sure SH is in this camp too, but I bet the syntax is yet 
again different.

> NOTE: When all instructions are 32-bits, there are not enough bits
> to have an opcode and the full 32-bit value.  I recall various
> RISC architectures limits around 14 bit constants. 


Yep.

Still doesn't offer an explanation to Ralf's original problem, where the 
newest gas appears to be choking on what used to be a perfectly valid 
instruction (albeit one that takes some work to turn into a valid opcode)...


b.g.

-- 
Bill Gatliff
Linux, NetBSD, RTEMS, eCos: yea, I do free software!
bgat at billgatliff.com