mips exception handling - help needed

[durai]

Hi,
I am working in a mips processor which doesnt implement some instructions
(lwl,lwr etc) and I wanted to emulate this instructions is exception
handler.

I am having a exception handler in linux with the following format.
----------------------------------------------------------------------------
--------------------------
void do_ri( struct pt_regs *regs )
{

....
.....
 branchDelay = ( ( 0 != ( regs->cp0_cause & CAUSEF_BD ) ) ||   (
isJumpInstruction( regs->cp0_epc ) ) );
......
........
 /*
      =====================================
      Get the instruction that caused this
      interrupt:
      =====================================
    */
    inst = *((unsigned long *)(regs->cp0_epc) + ( branchDelay ? 1 : 0 ));

//emulate the instruction

.............
}
----------------------------------------------------------------------------
--------------------------

How can I  implement that handler in RTEMS? to be more precise, I wanted to
know how to access the processor registers inside my exception handler, also
i wanted to know whether  the processor registers will be saved before
calling my exception handler. Will it be possible to to store the processor
registers before calling the exception handler, because i have to get the
instruction opcode from the stored registers and emulate it.

regards
durai