The maximum length of time interrupts are disabled

[Till Straumann]

You don't have to be concerned that the interrupt will be missed. All 
hardware
I know of does latch interrupts. This means that if an interrupt occurs 
while a
protected section is executed (interrupts disabled), the ISR will run 
just after
rtems_interrupt_enable() restores the interupt mask.

What people are concerned about it the "interrupt latency", i.e., the 
time that
elapses between a device pulling the interrupt line and the ISR executing.
Interrupt latency increases with the length of protected sections.

I recorded maximal interrupt latencies of a heavily loaded RTEMS system
running on a 300 MHz powerpc and found that the maximum latency recorded
during ~20*10 days (20 parallel systems) of operation with an IRQ rate 
of 4kHz
was about 20us.

-- Till

Fabrizio Sebastiani wrote:

> Hi all,
>     I have a question a general arch-indipendent question (Im using 
> sparc-rtems 4.0.0 for ERC32)
> about the maximum length of time interrupts are disabled, regarding 
> invocation of rtems_interrupt_{disable,enable} routines.
>     My question is how can I be sure that one critical section never 
> miss an interrupt?
>     Suppose to have such a tipical code:
>
> rtems_isr_level il;
>
> rtems_interrupt_disable(il);
> // ... critical section ....
> rtems_interrupt_enable(il);
>
>     Its clear to me that critical section have to perform the minimum 
> actions in order to be "fast";
>     Suppose that an interrupt comes while the CPU is executing the 
> critical section.
> How i can be sure that my critical section does not take too much time 
> before the re-enabling of the interrupt? How i can be sure that no 
> critical sections will
> miss some interrupt that was coming inside them?
>     I found some infos in the RTEMS docs:
>     For example, as explained in 
> http://www.rtems.com/onlinedocs/releases/4.0.0/doc/c_user/a00078.html
>     says that I should have a look at the spart architecture supplement:
> http://www.rtems.org/onlinedocs/releases/rtemsdocs-4.6.0/share/rtems/html/supplements/sparc/sparc00032.html
>     In this link there is only a statement that is obscure to me and 
> it doesnt seem to answer to my original question:
>
> "RTEMS has been optimized to insure that interrupts are disabled for 
> less than
> TBD microseconds on a 15.0 Mhz ERC32 with zero wait states.
> These numbers will vary based the number of wait states and processor 
> speed present on the target board.
> [NOTE:  The maximum period with interrupts disabled is hand calculated."
>
> have someone more infos/answers?
>
> tnks a lot ! :)
>
>
>
>