Is the Mips interrupt code flawed?

[Bruce Robinson]

To Mips-rtems users,

I found a knowledge base article on the PMC-Sierra's web site that describes
using a MIPS system call as the proper way to "atomically" disable
interrupts. The system call will cause the EXL flag to be set in the status
register, holding off interrupts while the IE bit is cleared. From my study
of the MIPS code, it appears that RTEMS disables interrupts by reading the
status register, adjusting the IP, EXL and IE flags, and then writing the
value back to the status register. Isn't it possible that an interceding
interrupt/context switch could result in the status register contents to be
incorrectly updated?

Am I missing something?

Any feedback would be appreciated!

Best Regards,
Bruce Robinson