Timing of events in an ISR

[Till Straumann]

Mark VanderVoord wrote:
> --- "Joel Sherrill <joel at OARcorp.com>"
> <joel.sherrill at OARcorp.com> wrote:
> 
> 
>>Can you verify that the task's do indeed have
>>interrupts
>>enabled AFTER the 1st interrupt occurs?  Random
>>thought
>>... if the ISR return path may not be restoring
>>interrupt
>>level correctly, it could accidentally disable
>>interrupts
>>in the interrupted thread.  Just periodically check
>>the
>>disable level in the threads.
> 
> 
> I've added a request for the task mode before and
> after the interrupt setup.  It is 127 in both places,
> even the first time it is run!  (It should be 0
> because I am running with RTEMS_DEFAULT_MODES).  I
> also checked at the very start of the routine.  It is
> also 127 here!
> 
> I've added a routine to set the mode from within the
> task to 0, then immediately check it.  It's again 127.

Again, it would help if you would attach your code.

I must stress that I'm not a mips person. However,
from looking at the context and _CPU_ISR_Get_level
related code, it seems that there is conditional
compilation involved when building RTEMS cpukit
("#if __mips == 3" ... "#elif __mips == 1")

Are you are sure your binary has been compiled
with the correct flags? Seems that it could make
a difference if you run __mips==1 compiled code
on a __mips==3 CPU.

Regarding the '127' mode -- it seems that this is OK.
The 8 'mode' bits are CPU specific. On the MIPS,
it seems that 0x7e correspond to the 6 hardware
interrupt lines (a 'one' means 'enabled') and bit
0x01 is a global 'enable'. Logically, a 'zero' mode
is mapped to 'all sources enabled', i.e., modes
127 and 0 are equivalent.

HTH
-- Till
> 
> This is true even if I do not initialize the SPI ISR
> to run.
> 
> I have never attempted to compile rtems before this
> point, but it looks like that is my only option at
> this point?
> 
> Mark S VanderVoord
> Self-Guided Systems, LLC
> 
> 
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